Assistant Professor
Computer Science and Engineering
School of Computing, Informatics, Decision Systems Engineering
Arizona State University


Other Work Experiences

High-Performance Cache Designs @ Intel Architecture Group, Intel Corp., Hudson, MA [9/2010 – 5/2011]

  • Proposed instruction-level, signature-based cache hit predictors to guide cache replacement.
  • Designed novel high-performing memory management techniques to improve cache utilization for multimedia, games, enterprise servers and scientific workloads.

Power Utilization Prediction for Data Center Workloads @ Platform Development, Google Inc., Mountain View, CA [6/2009 – 8/2009]

  • Developed a portfolio of application-level power prediction algorithms for Google data centers. This portfolio includes machine learning algorithms and linear regression techniques that exploit application CPU/power utilization history as well as algorithms that simply react to demand.
  • Analyzed Google benchmark and random CPU utilization traces sampled in production environment. Evaluated the effectiveness in prediction accuracy and the usability of the studied algorithms for representative workloads.

Performance and Scalability Characterization for Many-Core Systems @ Intel Lab, Intel Corp., Hillsboro, OR [6/2008 – 8/2008]

  • Analyzed performance and scalability issues related to System Management mode (SMM) on Intel’s many-core and Tera-scale platforms.

Visualization Software Development for Large-Scale Multicore Systems @ IBM TJ Watson Research Center,Hawthorne, NY [6/2007 – 8/2007]

  • Created a visualization software, Timeslice View, for large-scale multiprocessor systems in TuningFork.

Performance Characterization and Analysis @ Software Solution Group, Intel Corp., Chandler, AZ [5/2005 – 8/2005 and 8/2004 – 12/2004]

  • Profiled and characterized threading behaviors of various applications using Intel ThreadTracker, Thread Profiler and VTune performance analyzer.
  • Generated multi-threaded traces for IA32 pre-Si simulations for various applications, validated traces were representative, and performed pre-Si architectural analysis.
  • Built RT viewer, a graphical tool that characterizes threading behavior of an application in the pre-Si environment in a multi-core/multi-processor system.