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Seo_Jae-Sun_7064b_2

Jae-sun Seo, Assistant Professor
School of Electrical, Computer and Energy Engineering
Arizona State University

Contact Information
Office: ISTB4 551B
Address: 781 E Terrace Road, Tempe, AZ 85287
E-mail: jaesun.seo@asu.edu
Phone: (480) 727-2660

Latest news
June 2017:
Our paper titled “An Automatic RTL Compiler for High-Throughput FPGA Implementation of Diverse Deep Convolutional Neural Networks” is accepted for presentation at 2017 International Conference on Field-Programmable Logic and Applications (FPL 2017) in Ghent, Belgium.
May 2017:
Our paper titled ‘‘Triple-Mode, Hybrid-Storage Energy Harvesting Power Management Unit: Achieving High Efficiency against Harvesting and Load Variabilities’’ is accepted for publication in IEEE Journal of Solid-State Circuits (JSSC), special issue on 2016 Asian Solid-State Circuits Conference (collaboration with Columbia University).
May 2017:
Prof. Seo will serve as a panelist for the panel titled “Neuromorphic Computing and Deep Learning” at 2017 ACM/IEEE System Level Interconnect Prediction (SLIP) Workshop in Austin, TX.
May 2017: Prof. Seo will serve as the committee member for Student Research Preview at 2018 International Solid-State Circuits Conference (ISSCC).
May 2017:
Our paper titled “Improving Efficiency in Sparse Learning with the Feedforward Inhibitory Motif” is accepted for publication in Elsevier Neurocomputing (collaboration with UCR/UCSD).
May 2017:
Our paper titled “A 1.06 µW Smart ECG Processor in 65nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring“, which will be presented at 2017 IEEE Symposium on VLSI Circuits in June, is selected as one of the technical highlights of the conference, and included in the pre-conference press release kit [Symposium on VLSI link]. 
May 2017:
Our paper titled “Monolithic 3D IC Designs for Low-Power Deep Neural Networks Targeting Speech Recognition is accepted for presentation at 2017 IEEE International Symposium on Low Power Electronics and Design (ISLPED) in Taipei, Taiwan (collaboration with Georgia Institute of Technology).
April 2017:
Our paper titled “Designing ECG-based Physical Unclonable Function for Security of Wearable Devices is accepted for presentation at 2017 International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) in Jeju Island, Korea (collaboration with Samsung Advanced Institute of Technology).
April 2017:
Prof. Seo (with Prof. Rajendran at NJIT) will co-organize and present the tutorial titled “Towards the Ultimate Brain Computer – Hardware Designs of Artificial & Spiking Neural Networks“, held at 2017 International Joint Conference on Neural Networks (IJCNN 2017) in Anchorage, AK.
April 2017:
Prof. Seo (with Prof. Seok at Columbia Univ.) will co-organize a panel titled “Bio-inspired Learning and Inference Systems: What Works Well and What Didn’t “, held at 2017 IEEE Custom Integrated Circuits Conference (CICC) in Austin, TX.
March 2017
: Our paper titled “A 1.06 µW Smart ECG Processor in 65nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring” is accepted for presentation at 2017 IEEE Symposium on VLSI Circuits in Kyoto, Japan (collaboration with Samsung Advanced Institute of Technology).
March 2017: Prof. Seo receives National Science Foundation CAREER Award to study energy-efficient intelligent hardware [NSF link].
February 2017: Two of our papers are accepted for presentation at 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017) in Baltimore, MD.
– “End-to-End Scalable FPGA Accelerator for Deep Residual Networks
– “A Real-Time 17-Scale Object Detection Accelerator with Adaptive 2000-Stage Classification in 65nm CMOS” (collaboration with Zhejiang Univ.)
January 2017: Shihui Yin received the 2017 IEEE Solid-State Circuits Society Student Travel Grant  Award (STGA) and the 2017 IEEE Phoenix Section Student Scholarship Award.
November 2016
: Our paper titled “Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks” is accepted for presentation at 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017) in Monterey, CA.
November 2016: Our on-going biomedical hardware research will be presented by Shihui Yin at the Student Research Preview session at 2017 International Solid-State Circuits Conference (ISSCC) in San Francisco, CA.
November 2016: Our paper titled “Flying and Decoupling Capacitance Optimization for Area-Constrained On-Chip Switched-Capacitor Voltage Regulators” is accepted for presentation at 2017 Design, Test, and Automation in Europe (DATE 2017) in Lausanne, Switzerland (collaboration with Oracle Labs).
November 2016: There are 3 activities from our group at 2017 Asia and South Pacific Design Automation Conference (ASP-DAC) in Tokyo, Japan.
– Prof. Seo (together with Prof. Mingoo Seok @ Columbia Univ. and Prof. Zhengya Zhang @ Univ. of Michigan) will organize and present a tutorial titled “Towards Energy-Efficient
Intelligence in Power-/Area-Constrained Hardware
“.
– Our paper titled “A Real-time 17-Scale Object Detection Accelerator with Adaptive 2000-Stage Classification in 65nm CMOS” is accepted for presentation at the University LSI Design Contest (collaboration with Zhejiang Univ.).
– Our paper titled “Low-Power Neuromorphic Speech Recognition Engine with Coarse-Grain Sparsity” is invited for publication (collaboration with Univ. of Pittsburgh).
October 2016: Our paper titled “A Fixed-Point Neural Network Architecture For Speech Applications on Resource Constrained Hardware” is accepted for publication in Journal of Signal Processing Systems (JSPS) (collaboration with University of Michigan).
September 2016: Our paper titled “Bi-level Rare Temporal Pattern Detection” is accepted for presentation at 2016 IEEE International Conference on Data Mining (ICDM) as a regular paper (8.5% acceptance rate) in Barcelona, Spain.
September 2016: Prof. Seo will co-organize on the 2nd Workshop on Hardware and Algorithms for Learning On-a-Chip (HALO) held at 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), on November 10th in Austin, TX. The workshop will feature industry/academia presentations and discussions on efficient hardware designs of learning algorithms.
August 2016: Our paper titled “Triple-Mode Photovoltaic Power Management: Achieving High Efficiency against Harvesting and Load Variability” is accepted for presentation at 2016 IEEE Asian Solid-State Circuits Conference (ASSCC) in Toyoma, Japan (collaboration with Columbia University).
June 2016: Two of our papers are accepted for presentation at 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) in Austin, TX.
– “Efficient Memory Compression in Deep Neural Networks Using Coarse-Grain Sparsification for Speech Applications
– “Compact Oscillation Neuron Exploiting Metal-Insulator-Transition for Neuromorphic Computing
June 2016: Our paper titled “Scalable and Modularized RTL Compilation of Convolutional Neural Networks onto FPGA” is accepted for presentation at 2016 International Conference on Field-Programmable Logic and Applications (FPL 2016) in Lausanne, Switzerland.
June 2016: Prof. Seo (with Profs. Cao and Wang) will co-organize and give a presentation at a half-day tutorial titled “Energy-efficient Acceleration for Neuro-inspired Computing On-a-chip“, held at 2016 International Conference on Field-Programmable Logic and Applications (FPL 2016).
June 2016: Deepak Kadetotad and Shihui Yin have been awarded ICML (International Conference on Machine Learning) 2016 student scholarship (travel grant).
May 2016: Our whitepaper titled “Efficient Neuromorphic Learning with Motifs of Feedforward Inhibition” will be presented at Neuromorphic Computing (Architectures – Models – Applications) Workshop held at Oak Ridge National Laboratory.
May 2016: Two of our papers are accepted for presentation at ICML (International Conference on Machine Learning) 2016 Workshop on On-Device Intelligence.
– “Low-Power ECG Biometric Authentication for Wearable Systems Featuring Sparse Memory Compression”  (collaboration with Samsung Advanced Institute of Technology)
– “Efficient Memory Compression in Deep Neural Networks Using Coarse-Grain Sparsification for Speech Applications
April 2016: Our paper titled “Reducing the Model Order of Deep Neural Networks Using Information Theory” is invited for presentation at 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) in Pittsburgh, PA.
February 2016: Our paper titled “Thermoelectric-based Sustainable Self-Cooling for Fine-Grained Processor Hot Spots” will be presented at IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM 2016) in Las Vegas, NV.
January 2016: Our paper titled “Reducing Power, Leakage and Area of Standard Cell ASICs Using Threshold Logic Flipflopsis accepted for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
January 2016: Our paper titled “High-Performance Face Detection with CPU-FPGA Acceleration” will be presented at 2016 IEEE International Symposium on Circuits and Systems (ISCAS) in Montreal, Canada. 
December 2015: Our paper titled “Ranking the Parameters of Deep Neural Networks Using the Fisher Information” will be presented at 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) in Shanghai, China. 
December 2015: Our paper titled “A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering” is accepted for publication in IEEE Journal of Solid-State Circuits (JSSC), special issue on 2015 Symposium on VLSI Circuits (collaboration with Univ. of Michigan and IBM).
November 2015: Our paper titled “Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks” is accepted for presentation at 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2016) in Monterey, CA. 
October 2015: 
Our paper titled “Fully Parallel Write/Read in Resistive Synaptic Array for Accelerating On-Chip Learning” is published in Nanotechnology on IOPscience
September 2015: 
Our paper titled “On-Chip Sparse Learning Acceleration with CMOS and Resistive Synaptic Devices” is accepted for publication in IEEE Transactions on Nanotechnology (TNANO), special issue on “Cognitive and Natural Computing with Nanotechnology”.
August 2015
: Our paper titled “Digital CMOS Neuromorphic Processor Design Featuring Unsupervised Online Learning” is invited for presentation at 2015 IFIP/IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC) in Daejeon, Korea. (collaboration with Columbia Univ.)
August 2015: Prof. Seo will serve as the technical program committee on the Workshop on Hardware and Algorithms for Learning On-a-Chip (HALO) held at 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), on November 5th in Austin, TX. The workshop will feature industry/academia presentations and discussions on efficient hardware designs of learning algorithms.
July 2015: Our paper titled “Energy-Efficient Reconstruction of Compressively Sensed Bioelectrical Signals with Stochastic Computing Circuits” will be presented at 2015 IEEE International Conference on Computer Design (ICCD) in New York, NY.
June 2015: Our paper titled “Mitigating effects of non-ideal synaptic device characteristics for on-chip learning” will be presented at 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) in Austin, TX.
June 2015: Our paper titled “Dynamic and leakage power reduction of ASICs using configurable threshold logic gates” will be presented at 2015 IEEE Custom Integrated Circuits Conference (CICC) in San Jose, CA.
May 2015: Prof. Seo will serve as the publication chair for 2015 IEEE International Conference on Computer Design (ICCD).
April 2015: Three of our papers will be presented at 2015 IEEE International Symposium on Low Power Electronics and Design (ISLPED) in Rome, Italy.
– “A neuromorphic neural spike clustering processor for deep-brain sensing and stimulation systems” (collaboration with Columbia Univ.)
– “Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS
– “Analysis and optimization of CMOS switched-capacitor voltage converters” (collaboration with Univ. of Washington)
March 2015: Our paper titled “Parallel architecture with resistive crosspoint array for dictionary learning acceleration” is accepted for publication in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS).
March 2015: Prof. Seo will serve as the technical program committee (VLSI system track) for IoT Symposium at Embedded Systems Week on Nov. 2015 in Amsterdam, Netherlands. Researchers are encouraged to submit papers with IoT topics including ultra low energy systems, integrated sensors, and platform architectures.
March 2015: Our paper titled “A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple” will be presented at 2015 Symposium on VLSI Circuits in Kyoto, Japan (collaboration with IBM and Univ. of Michigan).
January 2015: Prof. Seo (with Profs. Ye, Cao, Vrudhula, Yu, He) will co-organize a workshop at SIAM International Conference on Data Mining (SDM15), on May 2015 in Vancouver, Canada. The workshop is titled “Adaptive Learning On-a-chip: Hardware and Algorithms (ALOHA)”, which will coordinate presentations and discussions by computational neuroscience, machine learning, and hardware design experts.
December 2014: Prof. Seo gives an invited talk on at Samsung Advanced Institute of Technology (SAIT) in Seoul, Korea.
November 2014: Our paper titled “Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip” will be presented at Design, Test, and Automation in Europe (DATE 2015) in Grenoble, France.
August 2014: Our paper “Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning” will be presented at 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS 2014) in Lausanne, Switzerland.
July 2014: Our paper titled “Parallel programming of resistive cross-point array for synaptic plasticity” will be presented at the Symposium on Biomorphic Circuits and Systems with Threshold Logic (BioTL 2014) in Boston, MA.
January 2014: Jae-sun Seo joined ASU as an assistant professor in the School of ECEE.