Publications

Book Chapters

Deepak Kadetotad, Pai-Yu Chen, Yu Cao, Shimeng Yu, and Jae-sun Seo, “Peripheral Circuit Design Considerations of Neuro-inspired Architectures,” Chapter in Neuro-inspired Computing Using Resistive Synaptic Devices, pp. 167-182, Springer International Publishing, 2017. [Springer link]

Journal Publications

Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Umit Y. Ogras, and Yu Cao, “Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs,IEEE Design & Test, 2020, accepted for publication. [IEEEXplore link]

Zhewei Jiang, Shihui Yin, Jae-sun Seo, and Mingoo Seok, “C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 7, pp. 1888-1897, July 2020. [Special Issue on 2019 ESSCIRC] [IEEEXplore link]

Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, and Jae-sun Seo, “An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 7, pp. 1877-1887, July 2020. [Special Issue on 2019 ESSCIRC] [IEEEXplore link]

Wonbo Shim, Yandong Luo, Jae-sun Seo, and Shimeng Yu, “Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM based Deep Learning Inference Engine,IEEE Transactions on Electron Devices, vol. 67, no. 6, pp. 2318-2323, June 2020. [IEEEXplore link]

Shihui Yin, Zhewei Jiang, Jae-sun Seo, and Mingoo Seok, “XNORSRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks,” IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 6, pp. 1733-1743, June 2020. [IEEEXplore link]

Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “Performance Modeling for CNN Inference Accelerators on FPGA,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 4, pp. 843-856, April 2020. [IEEEXplore link]

Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Gaurav Srivastava, Chisung Bae, Sang Joon Kim, and Jae-sun Seo, “ECG Authentication Hardware Design with Low-Power Signal Processing and Neural Network Optimization with Low Precision and Structured Compression, IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), vol. 14, no. 2, pp. 198-208, February 2020. [Special Section on AI-Based Biomedical Circuits and Systems] [IEEEXplore link]

Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “Automatic Compilation of Diverse CNNs onto High-Performance FPGA Accelerators,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 2, pp. 424-437, February 2020. [IEEEXplore link]

Shihui Yin and Jae-sun Seo, “A 2.6 TOPS/W 16-bit Fixed-Point Convolutional Neural Network Learning Processor in 65nm CMOS,” IEEE Solid-State Circuits Letters (SSC-L), vol. 3, no. 1, pp. 13-16, January 2020. [IEEEXplore link]

Shihui Yin, Zhewei Jiang, Minkyu Kim, Tushar Gupta, Mingoo Seok, and Jae-sun Seo, “Vesti: Ultra-Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks, IEEE Transactions on VLSI Circuits (TVLSI), vol. 28, no. 1, pp. 48-61, January 2020. [IEEEXplore link]

Shihui Yin, Yandong Luo, Yulhwa Kim, Wangxin He, Xu Han, Xiaoyu Sun, Hugh Barnaby, Jae-Joon Kim, Shimeng Yu, and Jae-sun Seo, “Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning,IEEE Micro, vol. 39, no. 6, pp. 54-63, November/December 2019. [IEEEXplore link]

Shihui Yin, Xiaoyu Sun, Shimeng Yu, and Jae-sun Seo, “High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS,ArXiv Preprint, arXiv:1909:07514, September 2019. [arXiv link]

Zhewei Jiang, Shihui Yin, Jae-sun Seo, and Mingoo Seok, “C3SRAM: In-Memory Computing SRAM Macro Based on Capacitive-Coupling Computing,” IEEE Solid-State Circuits Letters (SSC-L), vol. 2, no. 9, pp. 131-134, September 2019. [Special Issue on 2019 ESSCIRC] [IEEEXplore link]

Deepak Kadetotad, Visar Berisha, Chaitali Chakrabarti, and Jae-sun Seo, “A 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity with All Parameters Stored On-Chip,” IEEE Solid-State Circuits Letters (SSC-L), vol. 2, no. 9, pp. 119-122, September 2019. [Special Issue on 2019 ESSCIRC] [IEEEXplore link]

Shihui Yin, Minkyu Kim, Deepak Kadetotad, Yang Liu, Chisung Bae, Sang Joon Kim, Yu Cao, and Jae-sun Seo, “A 1.06 µW Smart ECG Processor in 65nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring,” IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 8, pp. 2316-2326, August 2019. [IEEEXplore link]

Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Luning Wei, Xiaofei He, Yu Cao, and Jae-sun Seo, “A Real-time 17-Scale Object Detection Accelerator with Adaptive 2000-Stage Classification in 65nm CMOS,” IEEE Transactions on Circuits and Systems I (TCAS-I), vol. 66, no. 10, pp. 3843-3853, June 2019. [IEEEXplore link]

Chetan S. Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun M. Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, and Ralph Etienne-Cummings, “Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain,” Frontiers of Neuroscience, vol. 12, pp. 891, December 2018. [Frontiers link]

Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, and Sung-Kyu Lim, “Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition,ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 14, no. 4, November 2018. [ACM link]

Robert D’Angelo, Xiaocong Du, Christopher D. Salthouse, Brent Hollosi, Geremy Freifeld, Wes Uy, Haiyao, Huang, Nhut Tran, Armand Chery, Jae-sun Seo, Yu Cao, Dorothy C. Poppe, and Sameer Sonkusale, “Process Scalability of Pulse Based Circuits for Analog Image Convolution,” IEEE Transactions on Circuits and Systems I (TCAS-I), vol. 65, no. 9, pp. 2929-2938, September 2018. [IEEEXplore link]

Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 7, pp. 1354-1367, July 2018. [IEEEXplore link]

Yufei Ma, Naveen Suda, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “ALAMO: FPGA Acceleration of Deep Learning Algorithms with a Modularized RTL Compiler,Integration, the VLSI Journal, vol. 62, pp. 14-23, June 2018. [ScienceDirect link]

Arindam Basu, Jyotibdha Acharya, Tanay Karnik, Huichu Liu, Hai Li, Jae-sun Seo, and Chang Song
Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 8, no. 1, pp. 6-27, March 2018. [IEEEXplore link]

Zihan Xu, Steven Skorheim, Ming Tu, Visar Berisha, Shimeng Yu, Jae-sun Seo, Maxim Bazhenov, and Yu Cao, “Improving Efficiency in Sparse Learning with the Feedforward Inhibitory Motif,” Neurocomputing, vol. 267, no. C, pp. 141-151, December 2017. [Elsevier link]

Jiangyi Li, Jae-sun Seo, Ioannis Kymissis, and Mingoo Seok, ‘‘Triple-Mode, Hybrid-Storage Energy Harvesting Power Management Unit: Achieving High Efficiency against Harvesting and Load Variabilities,’’ IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 10, pp. 2550-2562, October 2017. [Special Issue on 2016 ASSCC] [IEEEXplore link]

Mohit Shah, Sairam Arunachalam, Jingcheng Wang, David Blaauw, Dennis Sylvester, Hun-Seok Kim, Jae-sun Seo, and Chaitali Chakrabarti, “A Fixed-Point Neural Network Architecture For Speech Applications on Resource Constrained Hardware,” Journal of Signal Processing Systems, doi:10.1007/s11265-016-1202-x, 2016. [Springer link]

Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, and Sarma Vrudhula, “Reducing Power, Leakage and Area of Standard Cell ASICs Using Threshold Logic Flipflops,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2873-2886, September 2016. [IEEEXplore link]

Suyoung Bang, Jae-sun Seo, Leland Chang, David Blaauw, and Dennis Sylvester, “A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering,” IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 4, pp. 919-929, April 2016. [Special Issue on 2015 Symp. on VLSI Circuits] [IEEEXplore link]

Jae-sun Seo, Binbin Lin, Minkyu Kim, Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Sarma Vrudhula, Shimeng Yu, Jieping Ye, Yu Cao, “On-Chip Sparse Learning Acceleration with CMOS and Resistive Synaptic Devices,” IEEE Transactions on Nanotechnology (TNANO), vol. 14, no. 6, pp. 969-979, November 2015. [IEEEXplore link]

Ligang Gao, I-Ting Wang, Pai-Yu Chen, Sarma Vrudhula, Jae-sun Seo, Yu Cao, Tuo-Hung Hou, and Shimeng Yu, “Fully Parallel Write/Read in Resistive Synaptic Array for Accelerating On-Chip Learning,” Nanotechnology, vol. 26, 455204, October 2015. [IOPscience link]

Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma Vrudhula, Shimeng Yu, Yu Cao, and Jae-sun Seo, “Parallel Architecture with Resistive Crosspoint Array for Dictionary Learning Acceleration,” IEEE Journal on Emerging and
Selected Topics in Circuits and Systems (JETCAS), vol. 5, no. 2, pp. 194-204, June 2015. [IEEEXplore link]

Bipin Rajendran, Yong Liu, Jae-sun Seo, Kailash Gopalakrishnan, Leland Chang, Daniel Friedman, and Mark Ritter, “Specifications of Nanoscale Devices & Circuits for Neuromorphic Computational Systems,” IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 246-253, January 2013. [IEEEXplore link]

Jae-sun Seo, David Blaauw, and Dennis Sylvester, “Crosstalk-Aware PWM-Based On-Chip Links with Self-Calibration in 65nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), September 2011, vol. 46, no. 9, pp. 2041-2052, September 2011. [IEEEXplore link]

Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, and Ram Krishnamurthy, “A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 264-273, February 2011. [IEEEXplore link]

Jongwoo Lee, Joshua Kang, Sunghyun Park, Jae-sun Seo, Jens Anders, Jorge Guilherme, and Michael Flynn, “A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC,” IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 10, pp. 2755-2765, October 2009. [IEEEXplore link]

Prashant Singh, Jae-sun Seo, David Blaauw, and Dennis Sylvester, “Self-timed Regenerators for High-speed and Low-power Global Interconnects,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 6, pp. 673-677, June 2008. [IEEEXplore link]

Conference Publications

Xu Han, Aymeric Privat, Keith E. Holbert, Jae-sun Seo, Shimeng Yu, and Hugh Barnaby, “Total Ionizing Dose Effect on Multi-state HfOx-based RRAM Synaptic Array,IEEE Nuclear & Space Radiation Effects Conference (NSREC), December 2020, to appear.

Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Jae-sun Seo, Frank Liu, and Yu Cao, “Online Knowledge Acquisition with Selective Inherited Model,IEEE International Joint Conference on Neural Networks (IJCNN), July 2020, to appear.

Yandong Luo, Xiaochen Peng, Ryan Hatcher, Titash Rakshit, Jorge Kittl, Jae-sun Seo, and Shimeng Yu, “A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2020.

Wonbo Shim, Yandong Luo, Jae-sun Seo, and Shimeng Yu, “Impact of Read Disturb on Multi-level RRAM based Inference Engine: Experiments and Model Prediction,IEEE International Reliability Physics Symposium (IRPS), March 2020.

Shruti Kulkarni, Shihui Yin, Jae-sun Seo, and Bipin Rajendran, “An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays,IEEE Design, Automation & Test in Europe (DATE), March 2020. [IEEEXplore link]

Minkyu Kim and Jae-sun Seo, “Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access,IEEE Custom Integrated Circuits Conference (CICC), March 2020. [IEEEXplore link]

Shruti Kulkarni, Deepak Kadetotad, Shihui Yin, Jae-sun Seo, and Bipin Rajendran, “Neuromorphic Hardware Accelerator for SNN Inference Based on STT-Ram Crossbar Arrays,” IEEE International Conference on Electronics, Circuits and Systems, November 2019. [IEEEXplore link]

Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, and Jae-sun Seo, “A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key Generation,” IEEE Asian Solid-State Circuits Conference (A-SSCC), November 2019. [IEEEXplore link]

Zhewei Jiang Shihui Yin, Minkyu Kim, Tushar Gupta, Mingoo Seok, and Jae-sun Seo, “Vesti: Ultra-Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks,IEEE Asilomar Conference on Signals, Systems, and Computers, November 2019. [invited] [IEEEXplore link]

Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, and Shimeng Yu, “Inference Engine Benchmarking Across Technological Platforms from CMOS to RRAM,The International Symposium on Memory Systems (MEMSYS), October 2019. [ACM link]

Zhewei Jiang, Shihui Yin, Jae-sun Seo, and Mingoo Seok, “C3SRAM: In-Memory Computing SRAM Macro Based on Capacitive-Coupling Computing,” IEEE European Solid-State Circuits Conference (ESSCIRC), September 2019. [IEEEXplore link]

Deepak Kadetotad, Visar Berisha, Chaitali Chakrabarti, and Jae-sun Seo, “A 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity with All Parameters Stored On-Chip,IEEE European Solid-State Circuits Conference (ESSCIRC), September 2019. [IEEEXplore link]

Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvithadhi, Aravind Dasu, Yu Cao, and Jae-sun Seo, “Automatic Compiler Based FPGA Accelerator for CNN Training, International Conference on Field-Programmable Logic and Applications (FPL), September 2019. [IEEEXplore link] [Slides]

Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, and Jae-sun Seo, “K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2019. [IEEEXplore link]

Sai Kiran Cherupally, Gaurav Srivastava, Shihui Yin, Chisung Bae, Sang Joon Kim, and Jae-Sun Seo, “ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2019. [IEEEXplore link]

Zhewei Jiang, Shihui Yin, Jae-sun Seo, and Mingoo Seok, “XNOR-SRAM: In-Bitcell Computing SRAM Macro based on the Resistive Computing Mechanism,” ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2019. [invited] [ACM link]

Gaurav Srivastava, Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, and Jae-sun Seo, “Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks,IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), May 2019. [IEEEXplore link] [codes]

Mingoo Seok, Minhao Yang, Zhewei Jiang, Aurel. A. Lazar, Jae-sun Seo, “Cases for Analog-Mixed-Signal Computing Integrated-Circuits for Deep Neural Networks,” International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), April 2019. [invited] [IEEEXplore link]

Paul Whatmough, Chuteng Zhou, Patrick Hansen, Shreyas Venkataramanaiah, Jae-sun Seo, and Matthew Mattina, “FixyNN: Energy-Efficient Real-Time Mobile Computer Vision Hardware Acceleration via Transfer Learning,Conference on Systems and Machine Learning (SysML), April 2019. [SysML link

Yufei Ma, Tu Zheng, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “Algorithm-Hardware Co-Design of Single Shot Detector for Fast Object Detection on FPGAs,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2018. [ACM link

Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo, and Chaitali Chakrabarti, “A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks,” IEEE International Workshop on Signal Processing Systems (SiPS), October 2018. [IEEEXplore link]

Shruti R. Kulkarni, Deepak Kadetotad, Jae-sun Seo, and Bipin Rajendran, “Well-Posed Verilog-A Compact Model for Phase Change Memory,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2018. [IEEEXplore link]

Zhewei Jiang, Shihui Yin, Mingoo Seok, and Jae-sun Seo, “XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks,” IEEE Symposium on VLSI Circuits, June 2018. [IEEEXplore link]

Prad Kadambi, Abinash Mohanty, Hao Ren, Jaclyn Smith, Kevin McGuinnes, Kimberly Holt, Armin Furtwaengler, Roberto Slepetys, Zheng Yang, Jae-sun Seo, Sarma Vrudhula, Junseok Chae, Yu Cao, and Visar Berisha, “Towards a Wearable Cough Detector Based on Neural NetworksIEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), April 2018. [IEEEXplore link]

Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, and Shimeng Yu, “XNOR-RRAM: A Scalable and Parallel Synaptic Architecture for Binary Neural Networks,” Design, Automation & Test in Europe (DATE), March 2018. [IEEEXplore link]

Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, and Shimeng Yu, “Fully Parallel RRAM Synaptic Array for Implementing Binary Neural Network with (+1, -1) Weights and (+1, 0) Neurons,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018. [IEEEXplore link]

Abinash Mohanty, Xiaocong Du, Pai-Yu Chen, Jae-sun Seo, Shimeng Yu, and Yu Cao, “Random Sparse Adaptation for Accurate Inference with Inaccurate Multi-Level RRAM Arrays,” IEEE International Electron Devices Meeting (IEDM), December 2017. [IEEEXplore link]

Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, and Jae-sun Seo, “Minimizing Area and Energy of Deep Learning Hardware Design Using Binarization and Structured Compression,” Asilomar Conference on Signals, Systems, and Computers, October 2017. [invited] [arXiv link][IEEEXplore link]

Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, and Jae-sun Seo, “Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations,” IEEE Biomedical Circuits and Systems Conference (BioCAS), October 2017. [IEEEXplore link][arXiv link] [codes]

Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “An Automatic RTL Compiler for High-Throughput FPGA Implementation of Diverse Deep Convolutional Neural Networks,” IEEE International Conference on Field-Programmable Logic and Applications (FPL), September 2017. [IEEEXplore link]

Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo and Sung Kyu Lim, “Monolithic 3D IC Designs for Low-Power Deep Neural Networks Targeting Speech Recognition,ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2017. [IEEEXplore link]

Shihui Yin, Chisung Bae, Sang Joon Kim, and Jae-sun Seo, “Designing ECG-based Physical Unclonable Function for Security of Wearable Devices,” International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), July 2017. [IEEEXplore link]

Ricardo Tapiador-Morales, Antonio Rios-Navarro, Alejandro Linares-Barranco, Minkyu Kim, Deepak Kadetotad, and Jae-sun Seo, “Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs,” International Work-Conference on Artificial Neural Networks, pp. 271-282, June 2017. [Springer link]

Shihui Yin, Minkyu Kim, Deepak Kadetotad, Yang Liu, Chisung Bae, Sang Joon Kim, Yu Cao, and Jae-sun Seo, “A 1.06 µW Smart ECG Processor in 65nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring,” IEEE Symposium on VLSI Circuits, June 2017. [selected as one of the technical highlights] [IEEEXplore link]

Yufei Ma, Minkyu Kim, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “End-to-End Scalable FPGA Accelerator for Deep Residual Networks,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2017. [IEEEXplore link]

Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, and Jae-sun Seo, “A Real-time 17-Scale Object Detection Accelerator with Adaptive 2000-Stage Classification in 65nm CMOS,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2017. [IEEEXplore link]

Xiaoyang Mi, Hesam Fathi Moghadam, and Jae-sun Seo, “Flying and Decoupling Capacitance Optimization for Area-Constrained On-Chip Switched-Capacitor Voltage Regulators,” Design, Automation & Test in Europe (DATE), March 2017. [IEEEXplore link]

Yufei Ma, Yu Cao, Sarma Vrudhula, and Jae-sun Seo, “Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), February 2017. [ACM link] [Presentation slides]

Shihui Yin, Deepak Kadetotad, Bonan Yan, Chang Song, Yiran Chen, Chaitali Chakrabarti and Jae-sun Seo, “Low-Power Neuromorphic Speech Recognition Engine with Coarse-Grain Sparsity,” Asia and South Pacific Design Automation Conference (ASP-DAC), January 2017. [invited] [IEEEXplore link]

Dawei Zhou, Jingrui He, Yu Cao, and Jae-sun Seo, “Bi-level Rare Temporal Pattern Detection,” IEEE International Conference on Data Mining (ICDM), December 2016.