Publications

Total Citations: >4800  H-index: 31 (according to Google Scholar)

Journal papers          Conference papers

Book/Book chapters:

  1. S. Yu (Editor), Neuro-inspired Computing Using Resistive Synaptic Devices, Publisher: Springer, 2017. [Link]
  2. S. Yu, R. Liu, X. Sun, H. Wu, Y. Pang, B. Gao, H. Qian, A. Chen, “RRAM based hardware security primitives,” Security Opportunities by Nano Devices and Emerging Technologies, M. Tehranipoor, D. Forte, G. Rose, S. Bhunia (Eds.), Publisher: CRC Press/Taylor & Francis, 2017, in press.
  3. S. Yu, Resistive Random Access Memory (RRAM): From Devices to Array Architectures, Synthesis Lectures on Emerging Engineering Technologies 2 (5), 1-79, Publisher: Morgan & Claypool, 2016. [Link]
  4. R. Waser, D. Ielmini, H. Akinaga, H. Shima, H.-S. P. Wong, J. J. Yang, and S. Yu, “Introduction to nanoionic elements for information technology,” Resistive Switching: From Fundamentals of Nanoionic Redox Processes to Memristive Device Applications, D. Ielmini, R. Waser (Eds.), Publisher: Wiley, 2016.
  5. S. Yu, B. Lee, and H.-S. P. Wong, “Metal oxide resistive switching memory,” Functional Metal Oxide Nanostructures, J. Wu, J. Cao, W.-Q. Han, A. Janotti, H.-C. Kim, (Eds.), Publisher: Springer, 2011.

Journal papers:

  1. L. Gao, P.-Y. Chen, S. Yu, “NbOx based oscillation neuron for neuromorphic computing,” Appl. Phys. Lett., accepted.
  2. X. Sun, R. Liu, Y.-J. Chen, H.-Y. Chiu, W.-H. Chen, M.-F. Chang, S. Yu, “Low-VDD operation of SRAM synaptic array for implementing ternary neural network,” IEEE Trans. VLSI Systems, accepted.
  3. Z. Li, P.-Y. Chen, H. Xu, S. Yu, “Design of ternary neural network with 3D vertical RRAM array,” IEEE Trans. Electron Devices, vol. 64, no. 6, pp. 2721-2727, 2017.
  4. Z. Li, P.-Y. Chen, H. Liu, Q. Li, H. Xu, S. Yu, “Quasi-analytical model of 3D vertical RRAM array architecture for Mb-level design,” IEEE Trans. Electron Devices, vol. 64, no. 4, pp. 1568–1574, 2017.
  5. L. Gao, K. Holbert, S. Yu, “Total ionizing dose effects of gamma-ray radiation on NbOx based selector devices for crossbar array memory,” IEEE Trans. Nucl. Sci., vol. 64, no. 6, pp. 1535-1539, 2017.
  6. X. Peng, R. Madler, P.-Y. Chen, S. Yu, “Cross-point memory design challenges and survey of selector device characteristics,” Journal of Computational Electronics, accepted.
  7. W. Qian, P.-Y. Chen, R.  Karam, L. Gao, S. Bhunia, S. Yu, “Energy-efficient adaptive computing with multifunctional memory,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 2, pp. 191-195, 2017.
  8. M. Mao, P.-Y. Chen, S. Yu, C. Chakrabarti, “A multi-layer approach to designing energy-efficient and reliable ReRAM cross-point array system,” IEEE Trans. VLSI Systems, vol. 25, no. 5, pp. 1611-1621, 2017.
  9. Z. Xu, S. Skorheim, M. Tu, V. Berisha, S. Yu, J.-S. Seo, M. Bazhenov, Y. Cao, “Improving efficiency in sparse learning with the feedforward inhibitory motif,” Neurocomputing, accepted.
  10. A. Tosson, S. Yu, M. H. Anis, L. Wei, “A study of the effect of RRAM reliability soft errors on the performance of RRAM-based neuromorphic systems,” IEEE Trans. VLSI Systems, accepted.
  11. L. Xia, B. Li, T. Tang, P. Gu, P.-Y. Chen, S. Yu, Y. Cao, Y. Wang, Y. Xie, H. Yang, “MNSIM: simulation platform for memristor-based neuromorphic computing system,” IEEE Trans. CAD, accepted.
  12. Y. Pang, H. Wu, B. Gao, N. Deng, D Wu, R. Liu, S. Yu, A. Chen, H. Qian, “Optimization of RRAM-based physical unclonable function with a novel differential read-out method,” IEEE Electron Device Lett., vol. 38, no. 2, pp. 168-171, 2017.
  13. W. Wu, H. Wu, B. Gao, N. Deng, S. Yu, H. Qian, “Improving analog switching in HfOx based resistive memory with thermal enhanced layer,” IEEE Electron Device Lett., vol. 38, no. 8, pp. 1019-1022, 2017.

  14. S. Yu, P.-Y. Chen, “Emerging memory technologies: recent trends and prospects,” IEEE Solid State Circuits Magazine, vol. 8, no. 2, pp. 43-56, 2016, invited review. [Link]
  15. L. Gao, P.-Y. Chen, R. Liu, S. Yu, “Physical unclonable function exploiting sneak paths in resistive cross-point array,” IEEE Trans. Electron Devices, vol. 63, no. 8, pp. 3109-3115, 2016.
  16. L. Gao, P.-Y. Chen, S. Yu, “Demonstration of convolution kernel operation on resistive cross-point array,” IEEE Electron Device Lett., vol. 37, no. 7, 870-873, 2016.
  17. P.-Y. Chen, L. Gao, S. Yu, “Design of resistive synaptic array for implementing on-chip sparse learning,” IEEE Transactions on Multi-Scale Computing Systems, vol. 2, no. 4, pp. 257 – 264, 2016.
  18. P.-Y. Chen, Z. Li, S. Yu, “Design trade-offs of vertical RRAM based 3D cross-point array,”  IEEE Trans. VLSI Systems, vol. 24, no. 12, pp. 3460-3467, 2016. 
  19. R. Liu, H. Barnaby, S. Yu, “System-level analysis of single event upset susceptibility in RRAM architectures,” Semicond. Sci. Technol., vol. 31, no. 12, 124005, 2016.
  20. M. Mao, Y. Cao, S. Yu, C. Chakrabarti, “Optimizing latency, energy, and reliability of 1T1R ReRAM through cross-layer techniques,” IEEE J. Emerg. Sel. Topics Circuits Syst. (JETCAS), vol. 6, no. 3, 352-363, 2016.
  21. Z. Jiang, Y. Wu, S. Yu, L. Yang, K. Song, Z. Karim, and H.-S. P. Wong, “A compact model for metal oxide resistive random access memory (RRAM) with experiment verification,” IEEE Trans. Electron Devices, vol. 64, no. 5, pp. 1884-1892, 2016.
  22. Z. Chen, H. Li, H.-Y. Chen, B. Chen, R. Liu, P. Huang, F. Zhang, Z. Jiang, H. Ye, B. Gao, L. F. Liu, X. Y. Liu, J. F. Kang, H.-S. P. Wong, S.  Yu, “Disturbance characteristics of half-selected cells in cross-point resistive switching memory array,” Nanotechnology, vol. 27, 215204, 2016.
  23. L. Xia, P. Gu, B. Li, T. Tang, X. Yin, W. Huangfu, S. Yu, Y. Cao, Y. Wang, H. Yang, “Technological exploration of RRAM crossbar array for matrix-vector multiplication,” Journal of Computer Science and Technology, vol. 31, no. 1, pp. 3-19, 2016.

  24. R. Liu, H. Wu, Y. Pang, H. Qian, S. Yu, “Experimental characterization of physical unclonable function based on 1kb resistive random access memory arrays,” IEEE Electron Device Lett., vol. 36, no. 12, pp. 1380-1383, 2015.
  25. L. Gao, I-T. Wang, P.-Y. Chen, S. Vrudhula, J.-S. Seo, Y. Cao, T.-H. Hou, S. Yu, “Fully parallel write/read in resistive synaptic array for accelerating on-chip learning,” Nanotechnology, vol. 26, 455204, 2015.
  26. L. Gao, P.-Y. Chen, S. Yu, “Programming protocol optimization for analog weight tuning in resistive memories,” IEEE Electron Device Lett., vol. 36, no. 11, pp. 1157–1159, 2015.
  27. P.-Y. Chen, S. Yu, “Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design,” IEEE Trans. Electron Devices, vol. 62, no. 12, pp. 4022-4028, 2015.
  28. R. Liu, D. Mahalanabis, H. J. Barnaby, S. Yu, “Investigation of single-bit and multiple-bit upsets in oxide RRAM-based 1T1R and crossbar memory arrays,” IEEE Trans. Nucl. Sci., vol. 62, no. 5, pp. 2294-2301, 2015.
  29. R. Fang, W. Chen, L. Gao, W. Yu, S. Yu, “Low temperature characteristics of HfOx-based resistive random access memory,” IEEE Electron Device Lett., vol. 36, no. 6, pp. 567-569, 2015.
  30. D. Kadetotad, Z. Xu, A. Mohanty, P.-Y. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, J.-S. Seo, “Parallel architecture with resistive crosspoint array for dictionary learning acceleration,” IEEE J. Emerg. Sel. Topics Circuits Syst. (JETCAS),  vol. 5, no. 2, pp. 194-204, 2015.
  31. J.-S. Seo, B. Lin, M. Kim, P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, S. Vrudhula, S. Yu, J. Ye, Y. Cao, “On-chip sparse learning acceleration with CMOS and resistive synaptic devices,”  IEEE Trans. Nanotechnol., vol. 14, no. 6, pp. 969-979, 2015.
  32. D. Mahalanabis, R. Liu, H. J. Barnaby, S. Yu, M. N. Kozicki, A. Mahmud, and E. Deionno, “Single event susceptibility analysis in CBRAM resistive memory arrays,” IEEE Trans. Nucl. Sci., vol. 62, no. 6, pp. 2606-2612, 2015.
  33. W. Chen, H. J. Barnaby, M. N. Kozicki, A. H. Edwards, Y. Gonzalez-Velo, R. Fang, K. E. Holbert, S. Yu, W. Yu, “A study of gamma-ray exposure of Cu-SiO2 programmable metallization cells”, IEEE Trans. Nucl. Sci., vol. 62, no. 6, pp. 2404 – 2411, 2015.
  34. C. Xu, D. Niu, Y. Zheng, S. Yu, and Y. Xie, “Impact of cell failure on reliable cross-point resistive memory design,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 20, no. 4, article 63, 2015.
  35. H. Li, B. Gao, H.-Y. Chen, Z. Chen, P. Huang, R. Liu, L. Zhao, Z. Jiang, L. F. Liu, X. Y. Liu, S. Yu, J. F. Kang, Y. Nishi, and H.-S. P. Wong, “Three-dimensional resistive memory arrays: from intrinsic switching behaviors to optimization guidelines ,” IEEE Trans. Electron Devices, vol. 62, no. 10, pp. 3160-3167, 2015.

  36. R. Fang, Y. Gonzalez-Velo, W. Chen, K. Holbert, M. Kozicki, H. Barnaby, S. Yu, “Total ionizing dose effect of γ-ray radiation on the switching characteristics and filament stability of HfOx resistive random access memory,” Appl. Phys. Lett., 104, 183507, 2014.
  37. Z. Xu, A. Mohanty, P.-Y. Chen, D. Kadetotad, B. Lin, J. Ye, S. Vrudhula, S. Yu, J.-S. Seo, Y. Cao, “Parallel programming of resistive cross-point array for synaptic plasticity,” Procedia Computer Science, vol. 41, pp. 126-133, 2014.
  38. L. Zhao, H.-Y. Chen, S.-C. Wu, Z. Jiang, S. Yu, T.-H. Hou, H.-S. P. Wong, and Y. Nishi, “Multi-level control of conductive nano-filament evolution in HfO2 ReRAM by pulse-train operations,” Nanoscale, vol, 11, pp. 5698-5702, 2014.
  39. B. Gao, B. Chen, R. Liu, F. Zhang, P. Huang, L. F. Liu, X. Y. Liu, J. F. Kang, H.-Y Chen, S. Yu, and H.-S. P. Wong, “3D cross-point array operation on AlOy/HfOx based vertical resistive switching memory,” IEEE Trans. Electron Devices, vol. 61, no. 5, pp. 1377 – 1381, 2014.
  40. B. Gao, Y. Bi, H.-Y. Chen, R. Liu, P. Huang, B. Chen, L. F. Liu, X. Y. Liu, S. Yu, H.-S. P. Wong, J. F. Kang, “Ultra-low energy three-dimensional oxide-based electronic synapses for implementation of robust high accuracy neuromorphic computation systems,” ACS Nano, 2014, vol. 8, no. 7, pp. 6998-7004.

  41. S. Yu, B. Gao, Z. Fang, H. Y. Yu, J. F. Kang, and H.-S. P. Wong, “Stochastic learning in oxide binary synaptic device for neuromorphic computing,” Front. Neurosci., vol. 7, 186, 2013.
  42. H.-Y. Chen, S. Yu, B. Gao, R. Liu, Z. Jiang, Y. Deng, B. Chen, J. F. Kang, and H.-S. P. Wong, “Experimental study of plane electrode thickness scaling for 3D vertical resistive random access memory,” Nanotechnology, vol. 24, 465201, 2013.
  43. D. Kuzum, S. Yu, and H.-S. P. Wong, “Synaptic electronics: materials, devices and applications,” Nanotechnology, vol. 24, 382001, 2013, invited review.
  44. S. Yu, B. Gao, Z. Fang, H. Y. Yu, J. F. Kang, and H.-S. P. Wong, “A low energy oxide-based electronic synaptic device for neuromorphic visual system with tolerance to device variation,” Adv. Mater., vol. 25, no. 12, pp. 1774-1779, 2013.
  45. S. Yu, H.-Y. Chen, B. Gao, J. F. Kang, and H.-S. P. Wong, “A HfOx based vertical resistive switching random access memory for bit-cost-effective three-dimensional cross-point architecture,” ACS Nano, vol. 7, no. 3, pp. 2320-2325, 2013.
  46. H. Tian, H.-Y. Chen, B. Gao, S. Yu, J. Liang, Y. Yang, D. Xie, J. Kang, T.-L. Ren, Y. Zhang, and H.-S. P. Wong, “Monitoring oxygen movement by Raman spectroscopy of resistive random access memory with a graphene-inserted electrode,” Nano Lett., vol. 13, no. 2, pp. 651-657, 2013.

  47. X. Guan, S. Yu, and H.-S. P. Wong, “A SPICE compact model of metal oxide resistive switching memory with variations,” IEEE Electron Device Lett., vol. 33, no. 10, pp. 1405-1407, 2012.
  48. X. Guan, S. Yu, and H.-S. P. Wong, “On the switching parameter variation of metal oxide RRAM – part I: physical modeling and simulation methodology,” IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1172-1182, 2012.
  49. S. Yu, X. Guan, and H.-S. P. Wong, “On the switching parameter variation of metal oxide RRAM – part II: model corroboration and device design strategy,” IEEE Trans. Electron Devices, vol. 59 no. 4, pp. 1183-1189, 2012.
  50. S. Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, “Characterization of low-frequency noise in the resistive switching of transition metal oxide HfO2,” Phys. Rev. B, vol. 85, 045324, 2012.
  51. S. Yu, Y. Y. Chen, X. Guan, H.-S. P. Wong, J. A. Kittl, “A Monte Carlo study of the low resistance state retention of HfOx based resistive switching memory,” Appl. Phys. Lett., vol. 100, 043507, 2012.
  52. D. Kuzum, R. Jeyasingh, S. Yu, and H.-S. P. Wong, “Low energy, robust neuromorphic computation using synaptic devices,” IEEE Trans. Electron Devices, vol. 59, no. 12, pp. 3489-3494, 2012.
  53. H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F. T. Chen, and M.-J. Tsai, “Metal Oxide RRAM,” Proc. IEEE, vol. 100, no. 6, pp. 1951-1970, 2012, invited review.

  54. S. Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, “AC conductance measurement and analysis of the conduction processes in HfOx based resistive switching memory,” Appl. Phys. Lett., vol. 99, 232105, 2011.
  55. S. Yu, X. Guan, and H.-S. P. Wong, “Conduction mechanism of TiN/HfOx/Pt resistive switching memory: a trap-assisted-tunneling model,” Appl. Phys. Lett., vol. 99, 063507, 2011.
  56. S. Yu, Y. Wu, and H.-S. P. Wong, “Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory,” Appl. Phys. Lett., vol. 98, 103514, 2011.
  57. S. Yu, Y. Wu, R. Jeyasingh, D. Kuzum, and H.-S. P. Wong, “An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation”, IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2729-2737, 2011.
  58. S. Yu, and H.-S. P. Wong, “Compact modeling of conducting bridge random access memory (CBRAM),” IEEE Trans. Electron Devices, vol. 58, no. 5, pp. 1352-1360, 2011.
  59. Y. Wu, S. Yu, B. Lee, and H.-S. P. Wong, “Low-power TiN/Al2O3/Pt resistive switching device with sub-20 uA switching current and gradual resistance modulation,” J. Appl. Phys., vol. 110, 094104, 2011.
  60. Y. Chai, Y. Wu, K. Takei, H.-Y. Chen, S. Yu, P. C. H. Chan, A. Javey, and H.-S. P. Wong, “Nanoscale bipolar and complementary resistive switching memory based on amorphous carbon,” IEEE Trans. Electron Devices, vol. 58, no. 11, pp. 3933-3939, 2011.
  61. Y. Yang, S. Yu, L. Zeng, G. Du, J. F. Kang, Y. Zhao, R. Q. Han, and X. Y. Liu, “Variability induced by line edge roughness in double-gate dopant-segregated Schottky MOSFETs,” IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 244-249, 2011.

  62. S. Yu, and H.-S. P. Wong, “A phenomenological model for the reset mechanism of metal oxide RRAM,” IEEE Electron Device Lett., vol. 31, no. 12, pp.1455-1457, 2010.
  63. S. Yu, J. Liang, Y. Wu, and H.-S. P. Wong, “Read/write schemes analysis for the novel complementary resistive switches in passive crossbar memory arrays,” Nanotechnology, vol. 21, 465202, 2010.
  64. S. Yu, B. Gao, H. B. Dai, B. Sun, L. F. Liu, X. Y. Liu, R. Q. Han, J. F. Kang, and B. Yu, “Improved uniformity of resistive switching behaviors in HfO2 thin films with embedded Al layers,” Electrochem. Solid-State Lett., vol. 13, H36-H38, 2010.

  65. S. Yu, Y. Zhao, L. Zeng, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Impact of line edge roughness on double-gate Schottky barrier field-effect transistors,” IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1211-1219, 2009.
  66. S. Yu, Y. Zhao, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “The impact of line edge roughness on the stability of a FinFET SRAM,” Semicond. Sci. Technol., vol. 24, 025005, 2009.
  67. S. Yu, Y. Zhao, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Triple-gate FinFETs with fin-thickness optimization to reduce the impact of fin line edge roughness,” Jpn. J. Appl. Phys., vol.48, 04C052, 2009.

Conference papers:

  1. R. Liu, H.-Y. Lee, S. Yu, “Analyzing inference robustness of RRAM synaptic array in low-precision neural network,” IEEE European Solid-State Device Research Conference (ESSDERC) 2017, Leuven, Belgium.
  2. P.-Y. Chen, X. Peng, S. Yu, “System-level benchmark of synaptic device characteristics for neuro-inspired computing,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2017, San Francisco, USA, invited.
  3. R. Liu, H. Wu, Y. Pang, H. Qian, S. Yu, “Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module,” IEEE Asian Hardware-Oriented Security and Trust Symposium (AsianHOST) 2017, Beijing, China.
  4. R. Liu, P.-Y. Chen, S. Yu, “Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point Array,” IEEE International Symposium on Circuits and Systems (ISCAS) 2017, Baltimore, USA.
  5. L. Gao, P.-Y. Chen, S. Yu, “Exploiting NbOx metal-insulator-transition device as oscillation neuron for neuro-inspired computing,” IEEE Electron Devices Technology and Manufacturing (EDTM) 2017, Toyama, Japan.
  6. S. Yu, L. Gao, B. Dong, P.-Y. Chen, “Oscillation neuron device design considerations,” Materials Research Society (MRS) Spring Meeting 2017, Phoenix, USA, invited.
  7. A. Tosson, S. Yu, M. H. Anis, L. Wei, “Mitigating the effect of reliability soft-errors of RRAM devices on the performance of RRAM-based neuromorphic systems,” ACM Great Lakes Symposium on VLSI (GLSVLSI) 2017, Banff, Alberta, Canada.
  8. A. Tosson, S. Yu, M. H. Anis, L. Wei, “Analysis of RRAM reliability soft-errors on the performance of RRAM-based neuromorphic systems,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2017, Bochum, Germany.
  9. A. Tosson, S. Yu, M. H. Anis, L. Wei, “1T2R: a novel memory cell design to resolve single-event upset in RRAM arrays,” IEEE International Conference on ASIC (ASICON) 2017, Guiyang, China.
  10. P. Yao, H. Wu, B. Gao, N. Deng, S. Yu, H. Qian, “Online training on RRAM based neuromorphic network: experimental demonstration and operation scheme optimization,” IEEE Electron Devices Technology and Manufacturing (EDTM) 2017, Toyama, Japan.
  11. Y. Pang, H. Wu, B. Gao, R. Liu, S. Wang, S. Yu, A. Chen, H. Qian, “Design and optimization of strong physical unclonable function (PUF) based on RRAM array,” IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2017, Hsinchu, Taiwan.

  12. S. Yu, Z. Li, P.-Y. Chen, H. Wu, B. Gao, D. Wang, W. Wu, H. Qian, “Binary neural network with 16 Mb RRAM macro chip for classification and online training,” IEEE International Electron Devices Meeting (IEDM) 2016, San Francisco, USA. 
  13. P.-Y. Chen, J.-S. Seo, Y. Cao, S. Yu, “Compact oscillation neuron exploiting metal-
    insulator-transition for neuromorphic computing,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2016, Austin, TX, USA.
  14. L. Gao, P.-Y. Chen, S. Yu, “Weight tuning of resistive memories and convolution kernel operation on cross-point array for neuro-inspired computing,” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2016, Hangzhou, China, invited.
  15. R. Liu, H. Wu, Y. Pang, H. Qian, S. Yu, “A highly reliable and tamper-resistant RRAM PUF: design and experimental validation,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) 2016, Washington DC, USA.
  16. P.-Y. Chen, S. Yu, “Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing,” IEEE International Symposium on Circuits and Systems (ISCAS) 2016, Montreal, Canada.
  17. A. Shrivastava, P.-Y. Chen, Y. Cao, S. Yu, C. Chakrabarti, “Design of a reliable RRAM-based PUF for compact hardware security primitives,” IEEE International Symposium on Circuits and Systems (ISCAS) 2016, Montreal, Canada.
  18. Z. Xu, P.-Y. Chen, J.-S. Seo, S. Yu, Y. Cao, “Hardware-efficient learning with feedforward inhibition,” IEEE Nanoelectronics Conference (INEC) 2016, Chengdu, China, invited.
  19. L. Xia, B. Li, T. Tang, P. Gu, X. Yin, W. Huangfu, P.-Y. Chen, S. Yu, Y. Cao, Y. Wang, Y. Xie, H. Yang, “MNSIM: simulation platform for memristor-based neuromorphic computing system,” IEEE Design, Automation & Test in Europe (DATE) 2016, Dresden, Germany.
  20. Y. Cao, S. Yu, Y. Wang, P.-Y. Chen, L. Xia, H. Yang, “Neuromorphic computing with resistive synaptic arrays: devices, circuits and systems,” IEEE International Symposium on Quality Electronic Design (ISQED) 2016, Santa Clara, CA, USA, invited.
  21. R. Karam, R. Liu, P.-Y. Chen, S. Yu, and S. Bhunia, “Security primitive design with nanoscale devices: a case study with resistive RAM,” ACM Great Lakes Symposium on VLSI (GLSVLSI) 2015, Boston, USA, invited.
  22. L. Ceze, J. Hasler, K. K. Likharev, J.-S. Seo, T. Sherwood, D. Strukov, Y. Xie, S. Yu, “Nanoelectronic neurocomputing: status and prospects,” IEEE Device Research Conference (DRC) 2016, Newark, DE, USA, invited.

  23. S. Yu, P.-Y. Chen, Y. Cao, L. Xia, Y. Wang, H. Wu, “Scaling-up resistive synaptic arrays for neuro-inspired architecture: challenges and prospect,” IEEE International Electron Devices Meeting (IEDM) 2015, Washington DC, USA, invited. 
  24. S. B. Eryilmaz, D. Kuzum, S. Yu, H.-S. P. Wong, “Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures,” IEEE International Electron Devices Meeting (IEDM) 2015, Washington DC, USA, invited. 
  25. P.-Y. Chen, B. Lin, I.-T. Wang, T.-H. Hou, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, and S. Yu, “Mitigating effects of non-ideal synaptic device characteristics for on-chip learning,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2015, Austin, TX, USA. 
  26. L. Gao, S. Yu, “Programming protocol optimization for analog weight tuning in resistive memories,” IEEE Device Research Conference (DRC) 2015, Columbus, OH, USA.
  27. R. Fang, W. Chen, L. Gao, S. Yu, “Low temperature characteristics of HfOx-based resistive random access memory,” MRS Electronic Materials Conference (EMC) 2015, Columbus, OH, USA. 
  28. P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, S. Yu, “Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip,” IEEE Design, Automation & Test in Europe (DATE) 2015, Grenoble, France.
  29. P.-Y. Chen, R. Fang, R. Liu, C. Chakrabarti, Y. Cao, S. Yu, “Exploiting resistive cross-point array for compact design of physical unclonable function,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) 2015, Washington DC, USA.
  30. S. Zuloaga, R. Liu, P.-Y. Chen, and S. Yu, “Scaling 2-layer RRAM cross-point array towards 10 nm node: a device-circuit co-design, IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal.
  31. S. Yu, Y. Cao, “On-chip sparse learning with resistive cross-point array architecture,” ACM Great Lakes Symposium on VLSI (GLSVLSI) 2015, Pittsburgh, USA, invited.
  32. M. Mao, Y. Cao, S. Yu, and C. Chakrabarti, “Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings,” IEEE International Conference on Computer Design (ICCD) 2015, New York, USA.
  33. M. Mao, Y. Cao, S. Yu, and C. Chakrabarti, “Programming strategies to improve energy efficiency and reliability of ReRAM memory systems,” IEEE Workshop on Signal Processing Systems (SiPS) 2015, Hangzhou, China.
  34. W. Chen, H. J. Barnaby, M. N. Kozicki, Y. Gonzalez-Velo, R. Fang, K. Holbert, S. Yu, W. Yu, “A study of gamma-ray exposure of Cu-SiO2 programmable metallization cells,” IEEE Nuclear and Space Radiation Effects Conference (NSREC) 2015, Boston, USA.
  35. P. Gu, B. Li, T. Tang, S. Yu, Y. Cao, Y. Wang, H. Yang, “Technological exploration of RRAM crossbar array for matrix-vector multiplication,” Asia and South Pacific Design Automation Conference (ASP-DAC) 2015, Tokyo, Japan.
  36. C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, Y. Xie, “Overcoming the challenges of cross-point resistive memory architectures,” IEEE International Symposium on High Performance Computer Architecture (HPCA) 2015, San Francisco, USA. 
  37. C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, Y. Xie, “Design a high-performance main memory by overcoming the challenges of crossbar resistive memory architectures,” 6th Annual Non-Volatile Memories Workshop (NVMW) 2015, San Diego, USA.
  38. Z. Jiang, P. Huang, L. Zhao, S. Kvatinsky, S. Yu, X. Y. Liu, J. F. Kang, Y. Nishi, and H. -S. P. Wong, “Performance prediction of large-scale 1S1R resistive memory array using machine learning,” IEEE International Memory Workshop (IMW) 2015, Monterey, CA, USA.
  39. J. F. Kang, B. Gao, P. Huang, L. F. Liu, X. Y. Liu, S. Yu, H. Y. Yu, H.-S. P. Wong, “RRAM based synaptic devices for neuromorphic visual systems,” IEEE International Conference on Digital Signal Processing (DSP) 2015, Singapore, invited.

  40. P.-Y. Chen, and S. Yu, “Impact of vertical RRAM device characteristics on 3D cross-point array design,” IEEE International Memory Workshop (IMW) 2014, pp.127-130, Taipei, Taiwan.
  41. P.-Y. Chen, and S. Yu, “Design of heterojunction oxide stack for 3D RRAM cross-point array,” 5th Annual Non-Volatile Memories Workshop (NVMW) 2014, San Diego, USA.
  42. P.-Y. Chen, C. Xu, Y. Xie, and S. Yu, “3D RRAM design and benchmark with 3D NAND FLASH,” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2014, Guilin China, invited.  
  43. J. Yang, N. Kulkarni, S. Yu, and S. Vrudhula, “Integration of threshold logic gates with RRAM devices for energy efficient and robust operation,”  IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) 2014, Paris, France.
  44. D. Kadetotad, Z. Xu, A. Mohanty, P.-Y. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, J.-S. Seo, “Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning,” IEEE Biomedical Circuits and Systems Conference (Bio-CAS) 2014, Lausanne, Switzerland.
  45. C. Xu, P.-Y. Chen, D. Niu, Y. Zheng, S. Yu, and Y. Xie,  “Architecting 3D vertical resistive memory for next-generation storage systems,” International Conference on Computer-Aided Design (ICCAD) 2014, San Jose, USA.
  46. C. Xu, D. Niu, Y. Zheng, S. Yu, and Y. Xie, “Reliability-aware cross-point resistive memory design,” ACM Great Lakes Symposium on VLSI (GLSVLSI) 2014, pp. 145-150, Houston, USA.
  47. C. Xu, D. Niu, S. Yu, and Y. Xie, “Modeling and design analysis of 3D vertical resistive memory- a low cost cross-point architecture,” Asia and South Pacific Design Automation Conference (ASP-DAC) 2014, pp. 825-830, Singapore.
  48. H.-Y Chen, B. Gao, H. Li, R. Liu, P. Huang, Z. Chen, B. Chen, F. Zhang, L. Zhao, Z. Jiang, L. F. Liu, X. Y. Liu, J. F. Kang, S. Yu, Y. Nishi, and H.-S. P. Wong, “Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays,” Symposium on VLSI Technology (VLSI) 2014, pp. 196-197, Hawaii, USA.
  49. L. Zhao, H.-Y. Chen, S.-C. Wu, Z. Jiang, S. Yu, T.-H. Hou, H.-S. P. Wong, and Y. Nishi, “Improved multi-level control of RRAM using pulse-train programming,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2014, Hsinchu, Taiwan.
  50. R. Liu, H.-Y. Chen, H. Li, P. Huang, L. Zhao,  Z. Chen, F. Zhang, B. Chen, L. F. Liu, X. Y. Liu, B. Gao, S. Yu, Y. Nishi, H.-S. P. Wong, and J. F. Kang, “Impact of pulse rise time on programming of cross-point RRAM arrays,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2014, Hsinchu, Taiwan.
  51. H. Li, H.-Y. Chen, Z. Chen, B. Chen, R. Liu, G. Qiu, P. Huang, F. Zhang, Z. Jiang, B. Gao, L. F. Liu, X. Y. Liu, S. Yu, H.-S. P. Wong, and J. F. Kang, “Write disturb analyses on half-selected cells of cross-point RRAM arrays,” International Reliability Physics Symposium (IRPS), 2014, Waikoloa, HI, USA.
  52. H. Li, Z. Jiang, P. Huang, H.-Y. Chen, B. Chen, R. Liu, Z. Chen, F. Zhang, L. F. Liu, Bi. Gao1, X. Y. Liu, S. Yu, H.-S. P. Wong, and J. F. Kang, “Statistical assessment methodology for the design and optimization of cross-point RRAM arrays,” IEEE International Memory Workshop (IMW) 2014, Taipei, Taiwan.
  53. Z. Jiang, S. Yu, Y. Wu, J. H. Engel, X. Guan, H.-S. P. Wong, “Verilog-A implementation of RRAM compact model for design of selector device,” IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2014, Yokohama, Japan.
  54. H.-Y. Chen, M. ShulakerS. Yu, H. Wei, B. Gao, J. Kang, S. Mitra, and H.-S. P. Wong, “Monolithic 3D integration of logic and memory,” 16th ACM/IEEE System Level Interconnect Prediction (SLIP) 2014, San Francisco, USA, invited.
  55. S. Yu, Y. Wu, H.-Y. Chen, Z. Jiang, J. Sohn, H.-S. P. Wong, “Metal–oxide-based resistive switching memory (RRAM): modeling, scaling, and 3D integration,” Materials Research Society (MRS) Spring Meeting  2014, San Francisco, USA, invited. 
  56. S. Yu, “Overview of resistive switching memory (RRAM) switching mechanism and device modeling,” IEEE International Symposium on Circuits and Systems (ISCAS) 2014, Melbourne, Australia, invited.
  57. S. Yu, D. Kuzum, and H.-S. P. Wong, “Design considerations of synaptic device for neuromorphic computing,” IEEE International Symposium on Circuits and Systems (ISCAS) 2014, Melbourne, Australia, invited.
  58. S. Yu, “Orientation classification by a winner-take-all network with oxide RRAM based synaptic devices,” IEEE International Symposium on Circuits and Systems (ISCAS) 2014, Melbourne, Australia, invited.
  59. S. Yu, Y. Deng, B. Gao, P. Huang, B. Chen, X. Y. Liu, J. F. Kang, H.-Y. Chen, Z. Jiang, and H.-S. P. Wong, “Design guidelines for 3D RRAM cross-point architecture,” IEEE International Symposium on Circuits and Systems (ISCAS) 2014, Melbourne, Australia, invited.
  60. J. F. Kang, B. Gao, B. Chen, P. Huang, F. F. Zhang, X. Y. Liu, H.-Y. Chen, Z. Jiang, H.-S. P. Wong, S. Yu, “Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture,” IEEE International Symposium on Circuits and Systems (ISCAS) 2014, Melbourne, Australia, invited.
  61. J. F. Kang, B. Gao, Y. J. Bi,  B. Chen, X. Y. Liu, S. Yu, H.-Y. Chen, and H.-S. P. Wong, “TMO-based memristive devices and application for neuromorphic systems,” 13th International Conference on Modern Materials and Technologies (CIMTEC) 2014, Montecantini Terme, Italy, invited.
  62. J. F. Kang, B. Gao, B. Chen, P. Huang1 F. F. Zhang, Y. Deng, L. F. Liu, X. Y. Liu, H.-Y. Chen, Z. Jiang, S. Yu, H.-S. P. Wong, “3D RRAM: design and optimization,” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2014, Guilin, China, invited.

  63. Y. Deng, H.-Y. Chen, B. Gao, S. Yu, S.-C. Wu, L. Zhao, B. Chen, Z. Jiang, X. Y. Liu, T.-H. Hou, Y. Nishi, J. F. Kang, and H.-S. P. Wong, “Design and optimization methodology for 3D RRAM arrays,” IEEE International Electron Devices Meeting (IEDM) 2013,  pp. 629-632, Washington DC, USA. 
  64. S. Yu, and H.-S. P. Wong, “Characterization and modeling of the conduction and switching mechanism of HfOx based RRAM,” Materials Research Society (MRS) Fall Meeting 2013, Boston, USA, invited.
  65. H. Yi, Y. Wu, Z. Zhang, H.-Y. Chen, S. Yu, and H.-S. P. Wong, “Metal oxide resistive switching memory (RRAM): devices, fabrication, and self-assembly patterning for random logic and memory devices (SRAM, NAND, RRAM),” 26th International Microprocesses and Nanotechnology Conference (MNC) 2013, Hokkaido, Japan, invited.
  66. Y. Wu, S. Yu, H.-Y. Chen, J. Liang, Z. Jiang, and H.-S. P. Wong, “Resistive switching random access memory (RRAM): materials, device, scaling, and array design,” 60th International Symposium of the American Vacuum Society (AVS) 2013, Long Beach, CA, USA, invited.
  67. H.-Y. Chen, S. Yu, Y. Wu, and H.-S. P. Wong, “3D vertical RRAM architecture and electrode/oxide interface engineering for next generation mass storage,” International Conference on Solid State Devices and Materials (SSDM) 2013, Fukuoka, Japan, invited.
  68. S. Yu, H.-Y. Chen, Y. Deng, B. Gao, Z. Jiang, J. F. Kang, and H.-S. P. Wong, “3D vertical RRAM – scaling limit analysis and demonstration of 3D array operation,” Symposium on VLSI Technology (VLSI) 2013, pp. 158-159, Kyoto, Japan.
  69. D. Kuzum, R. J. D. Jeyasingh, S. B. Eryilmaz, S. Yu, and H.-S. P. Wong, “Programming phase change synaptic devices for neuromorphic computation,” Materials Research Society (MRS) Spring Meeting 2013, San Francisco, USA, invited.
  70. C.-S. Lee, S. Yu, X. Guan, J. Luo, L. Wei, and H.-S. P. Wong, “Compact models of emerging devices,” IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) 2013, Hong Kong, invited.

  71. S. Yu, B. Gao, Z. Fang, H. Y. Yu, J. F. Kang, and H.-S. P. Wong, “A neuromorphic visual system using RRAM synaptic devices with sub-pJ energy and tolerance to variability: experimental characterization and large-scale modeling,” IEEE International Electron Devices Meeting (IEDM) 2012, pp. 239-242, San Francisco, USA.
  72. S. Yu, X. Guan, and H.-S. P. Wong, “Understanding metal oxide RRAM current overshoot and reliability using Kinetic Monte Carlo simulation,” IEEE International Electron Devices Meeting (IEDM) 2012, pp. 585-588, San Francisco, USA.
  73. H.-Y. Chen, S. Yu, B. Gao, P. Huang, J. F. Kang, and H.-S. P. Wong, “HfOx based vertical RRAM for cost-effective 3D cross-point architecture without cell selector,” IEEE International Electron Devices Meeting (IEDM) 2012, pp. 497-500, San Francisco, USA.
  74. H.-Y. Chen, H. Tian, B. Gao, S. Yu, J. Liang, J. Kang, Y. Zhang, T.-L. Ren, and H.-S. P. Wong, “Electrode/oxide interface engineering by inserting single-layer graphene: application for HfOx-based resistive random access memory,” IEEE International Electron Devices Meeting (IEDM) 2012, pp. 489-492, San Francisco, USA.
  75. Y. Wu, S. Yu, H.-S. P. Wong, Y.-S. Chen, H.-Y. Lee, S.-M. Wang, P.-Y. Gu, F. Chen, and M.-J. Tsai, “AlOx-based resistive switching device with gradual resistance modulation for neuromorphic device application,” IEEE International Memory Workshop (IMW) 2012, pp. 111-114, Milan, Italy.
  76. H.-S. P. Wong, X. Guan, D. Kuzum, R. Jeyasingh, and S. Yu, “Variability in emerging memory devices: physical understanding, modeling, and mitigation,” IEEE Workshop on Variability Modeling and Characterization (VMC) 2012, San Jose, USA, invited.
  77. Y. Wu, J. Liang, S. Yu, X. Guan, and H.-S. P. Wong, “Resistive switching random access memory – materials, device, interconnects, and scaling considerations,” IEEE International Integrated Reliability Workshop (IIRW) 2012, Lake Tahoe, USA, invited.
  78. Y. Wu, S. Yu, X. Guan, and H.-S. P. Wong, “Recent progress of resistive switching random access memory (RRAM),” IEEE Silicon Nanoelectronics Workshop (SNW) 2012, Hawaii, USA, invited.
  79. X. Guan, S. Yu, and H.-S. P. Wong, “On the variability of HfOx RRAM: from numerical simulation to compact modeling,” IEEE Workshop on Compact Modeling (WCM) 2012, Santa Clara, CA, USA, invited.

  80. S. Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, “Understanding the conduction and switching mechanism of metal oxide RRAM through low frequency noise and AC conductance measurement and analysis,” IEEE International Electron Devices Meeting (IEDM) 2011, pp. 275-278, Washington DC, USA.
  81. S. Yu, X. Guan, and H.-S. P. Wong, “On the stochastic nature of resistive switching in metal oxide RRAM: physical modeling, Monte Carlo simulation, and experimental characterization,” IEEE International Electron Devices Meeting (IEDM) 2011, pp. 413-416, Washington DC, USA.
  82. S. Yu, Y. Wu, Y. Chai, J. Provine and H.-S. P. Wong, “Characterization of switching parameters and multilevel capability in HfOx/AlOx bi-layer RRAM devices,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2011, pp. 106-107, Hsinchu, Taiwan.
  83. Y. Wu, Y. Chai, H.-Y. Chen, S. Yu, and H.-S. P. Wong, “Resistive switching AlOx-based memory with CNT electrode for ultra-low switching current and high density memory application,” Symposium on VLSI Technology (VLSI) 2011, pp. 26-27, Kyoto, Japan.
  84. H.-S. P. Wong, S. Kim, B. Lee, M. A. Caldwell, J. Liang, Y. Wu, R. Jeyasingh, and S. Yu, “Recent progress of phase change memory (PCM) and resistive switching random access memory (RRAM),” IEEE International Memory Workshop (IMW) 2011, pp. 10-14, Monterey, USA, invited.

  85. S. Yu, and H.-S. P. Wong, “Modeling the switching dynamics of programmable-metallization cell (PMC) memory and its application as synapse device for a neuromorphic computation system,” IEEE International Electron Devices Meeting (IEDM) 2010, pp. 520-523, San Francisco, USA.
  86. Y. Chai, Y. Wu, K. Takei, H.-Y. Chen, S. Yu, P. C. H. Chan, A. Javey, and H.-S. P. Wong, “Resistive switching of carbon-based RRAM with CNT electrodes for ultra-dense memory,” IEEE International Electron Devices Meeting (IEDM) 2010, pp. 214-217, San Francisco, USA.
  87. S. Yu, and H.-S. P. Wong, “A phenomenological model of oxygen ion transport for metal oxide resistive switching memory,” IEEE International Memory Workshop (IMW) 2010, pp. 54-57, Seoul, Korea.
  88. H.-S. P. Wong, S. Kim, B. Lee, M. A. Caldwell, J. Liang, Y. Wu, R. Jeyasingh, and S. Yu, “Recent progress of phase change memory (PCM) and resistive switching random access memory (RRAM),” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2010, pp. 1055-1060, Shanghai, China, invited.
  89. Y. Wu, S. Yu, B. Lee and H.-S. P. Wong, “Gradual set and reset in TiN/Al2O3/Pt resistive switching device with sub-20 uA current,” Materials Research Society (MRS) Fall Meeting 2010, paper K4.2, Boston, USA.

  90. S. Yu, Y. Zhao, L. Zeng, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Variability induced by line edge roughness in double-gate dopant-segregated Schottky MOSFETs,” IEEE Silicon Nanoelectronics Workshop (SNW) 2009, Kyoto Japan, pp.39-40, Kyoto, Japan.
  91. B. Gao, H. W. Zhang, S. Yu, B. Sun, L. F. Liu, X. Y. Liu, Y. Wang, R. Q. Han, J. F. Kang, B. Yu, and Y. Y. Wang, “Oxide-based RRAM: uniformity improvement using a new material-oriented methodology,” Symposium on VLSI Technology (VLSI) 2009, pp. 30-31, Kyoto, Japan.
  92. H. W. Zhang, B. Gao, S. Yu, L. Lai, L. Zeng, B. Sun, L. F. Liu, X. Y. Liu, J. Lu, R. Q. Han, and J. F. Kang, “Effects of ionic doping on the behaviors of oxygen vacancies in HfO2 and ZrO2: a first principles study,” IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2009, pp. 155-158, San Diego, USA.

  93. S. Yu, Y. Zhao, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Triple-gate FinFETs with fin-thickness optimization to reduce the impact of fin line edge roughness,” International Conference on Solid State Devices and Materials (SSDM) 2008, pp.440-441, Tsukuba, Japan.
  94. S. Yu, Y. Zhao, Y. Song, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “3-D simulation of geometrical variations impact on nanoscale FinFETs,” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2008. pp.408-411, Beijing, China.
  95. S. Yu, Y. Zhao, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Impact of stochastic mismatch on FinFETs SRAM induced by process variation,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2008, paper 4A-3, Hong Kong.
  96. B. Gao, S. Yu, N. Xu, L. F. Liu, B. Sun, X. Y. Liu, R. Q. Han, J. F. Kang, B. Yu, and Y. Y. Wang, “Oxide-based RRAM switching mechanism: A new ion-transport-recombination model,” IEEE International Electron Devices Meeting (IEDM) 2008, pp. 563-566, San Fransisco, USA.
  97. Y. He, Y. Zhao, S. Yu, C. Fan, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Impact of strain on the performance of Ge-Si core-shell nanowire field effect transistors,” IEEE International Electron Devices Meeting (IEDM) 2008, pp. 189-192, San Fransisco, USA.
  98. Y. Zhao, Y. He, S. Yu, C. Fan, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Impact of strain on phonon limited mobility in III-V core-shell nanowire,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2008, paper 6B-3, Hong Kong.
  99. S. Yu, Y. Zhao, Y. Song, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs,” IEEE Silicon Nanoelectronics Workshop (SNW) 2008, paper P1-10, Hawaii, USA.