{"id":1513,"date":"2023-07-03T19:25:58","date_gmt":"2023-07-03T23:25:58","guid":{"rendered":"https:\/\/www.ece.jhu.edu\/dfan\/?page_id=1513"},"modified":"2026-04-24T04:12:49","modified_gmt":"2026-04-24T04:12:49","slug":"conference-proceedings","status":"publish","type":"page","link":"https:\/\/faculty.engineering.asu.edu\/dfan\/conference-proceedings\/","title":{"rendered":"Conference Proceedings"},"content":{"rendered":"\n

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  1. [WACV\u201926<\/strong>] Yongjae Lee, Zhaoliang Zhang, and Deliang Fan, “SafeguardGS: 3D Gaussian Primitive Pruning While Avoiding Catastrophic Scene Destruction”\u00a0IEEE\/CVF Winter Conference on Applications of Computer Vision (WACV), Tucson, Arizona,\u00a0USA, March 6-10, 2026 [paper<\/a>] [code<\/a>] [video<\/a>]<\/li>\n\n\n\n
  2. [ESSERC\u201925<\/strong>] Amitesh Sridharan, Asmer Hamid Ali, Yongjae Lee, Anupreetham Anupreetham, Yaotian Liu, Jeff Zhang, Jae-sun Seo, and Deliang Fan, \u201cSAFER: Sparsity Integrated Processing-in-Memory Ai Accelerator with a Fused Dot-Product Engine and a RISC-V CPU,\u201d 51st European Solid-State Electronics Research Conference (ESSERC)<\/em>, Munich, Germany, Sep. 8-11, 2025 [pdf]<\/a><\/li>\n\n\n\n
  3. [USENIX Security\u201925]<\/strong>  Juyang Bai, Md Hafizul Islam Chowdhuryy, Jingtao Li, Fan Yao, Chaitali Chakrabarti, and Deliang Fan, \u201cPhantom: Privacy-Preserving Deep Neural Network Model Obfuscation in Heterogeneous TEE and GPU System\u201d In 34th USENIX Security Symposium<\/em>, Seattle, WA, USA, August 13\u201315, 2025 [pdf<\/a>] [code<\/a>] [project page<\/a>]<\/li>\n\n\n\n
  4. [ISLPED\u201925]<\/strong>  Ziyi Zhao, Qifeng Chen, Jingtao Li, Deliang Fan, Chaitali Chakrabarti, \u201cTEE-SFL: Time and Energy-efficient solution for addressing communication heterogeneity in Split Federated Learning Schemes,\u201d In <\/em>International Symposium on Low Power Electronics and Design (ISLPED), Iceland, Aug. 6-8, 2025 [pdf<\/a>]<\/li>\n\n\n\n
  5. [COINS\u201925]<\/strong>  Jingxing Li, Yongjae Lee, Abhay Kumar Yadav, Cheng Peng, Rama Chellappa, Deliang Fan, \u201cSpeedy MASt3R,\u201d In IEEE International Conference on Omni-layer Intelligent systems<\/em> (COINS), Madison, Wisconsin, USA, Aug. 4-6, 2025 (invited paper) [pdf<\/a>] [code<\/a>]<\/li>\n\n\n\n
  6. [GLSVLSI’25<\/strong>] Asmer Ali, Amitesh Sridharan, Cheng Guo, William Hwang, Wilman Tsai, Jeff Zhang, Yiran Chen, Shan X. Wang, Deliang Fan, “FP-SMR: A Fully Digital Floating-Point Processing-in-SAS-MRAM for Session-based Recommender System”, Great Lakes Symposium on VLSI (GLSVLSI), June 30 – July 2, 2025, New Orleans, LA, USA, 2025 [pdf<\/a>]<\/li>\n\n\n\n
  7. [GLSVLSI’25<\/strong>] Jingkai Guo, Asmer Ali, Li Yang and Deliang Fan, ” LoRAFusion: A Crossbar-aware Multi-task Adaption Framework  via Efficient Fusion of Pretrained LoRA Modules” Great Lakes Symposium on VLSI (GLSVLSI), June 30 – July 2, 2025, New Orleans, LA, USA, 2025 [pdf<\/a>] [code<\/a>]<\/li>\n\n\n\n
  8. [CVPR\u201925<\/strong>] Jian Meng, Ahmed Hasssan, Li Yang, Deliang Fan, Jinwoo Shin, and Jae-sun Seo, \u201cClosest Neighbors are Harmful for Lightweight Masked Auto-encoders\u201d IEEE\/CVF Conference on Computer Vision and Pattern Recognition (CVPR)<\/em>, Nashville TN, June 11 -15, 2025 [pdf<\/a>] [video<\/a>]<\/li>\n\n\n\n
  9. [ISQED\u201925]<\/strong>  Li Yang, Sen Lin, Fan Zhang, Junshan Zhang, and Deliang Fan, \u201cEfficient Self-Supervised Continual Learning with Progressive Task-correlated Layer Freezing,\u201d In <\/em>26th<\/sup> International Symposium on Quality Electronic Design (ISQED’25), San Francisco, CA, April 23-25, 2025 [pdf<\/a>]<\/li>\n\n\n\n
  10. [WACV\u201925<\/strong>] Yongjae Lee, Li Yang, and Deliang Fan, \u201cMFNeRF: Memory Efficient NeRF with Mixed-Feature Hash Table\u201d IEEE\/CVF Winter Conference on Applications of Computer Vision (WACV), Tucson, Arizona, USA, 2025 [pdf]<\/a> [video<\/a>] [code<\/a>]<\/li>\n\n\n\n
  11. [ASPDAC\u201925<\/strong>] Asmer Hamid Ali, Fan Zhang, Li Yang and Deliang Fan, \u201cLearning to Prune and Low-Rank Adaptation for Compact Language Model Deployment\u201d 30th Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, 2025 [pdf<\/a>]<\/li>\n\n\n\n
  12. [CCWC\u201925<\/strong>] Adnan Siraj Rakin, Li Yang, Jingtao Li, Fan Yao, Chaitali Chakrabarti, Yu Cao, Jae-sun Seo, and Deliang Fan, \u201cRA-BNN: Constructing a Robust & Accurate Binary Neural Network Using a Novel Network Growth Mechanism to Defend Against BFA\u201d IEEE 15th Annual Computing and Communication Workshop and Conference (CCWC), Las Vegas, NV, USA, Jan. 2025 [pdf<\/a>]<\/li>\n\n\n\n
  13. [NeurIPS\u201924<\/strong>] Zhaoliang Zhang, Tianchen Song, Yongjae Lee, Li Yang, Cheng Peng, Rama Chellappa, and Deliang Fan, \u201cLP-3DGS: Learning to Prune 3D Gaussian Splatting,\u201d Thirty-Eighth Conference on Neural Information Processing Systems (NeurIPS)<\/em>, Vancouver, Canada, Dec 16, 2024, Dec. 2024 [pdf]<\/a> [video<\/a>] [open source code<\/a>]<\/li>\n\n\n\n
  14. [DAC\u201924<\/strong>] Fan Zhang, Amitesh Sridharan, Wilman tsai, Yiran Chen, Shan X. Wang and Deliang Fan, \u201cEfficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Sparse On-Device Learning\u201d In: 61st Design Automation Conference (DAC)<\/em>, San Francisco, CA, June 23-27, 2024 [pdf<\/a>]<\/li>\n\n\n\n
  15. [DAC\u201924<\/strong>] Fan Zhang, Li Yang and Deliang Fan, \u201cHyb-Learn: A Framework for On-Device Self-Supervised Continual Learning with Hybrid RRAM\/SRAM Memory\u201d In: 61st Design Automation Conference (DAC)<\/em>, San Francisco, CA, June 23-27, 2024 [pdf<\/a>]<\/li>\n\n\n\n
  16. [DAC\u201924<\/strong>] Qilin Zheng, Ziru Li, Jonathan Ku, Yitu Wang, Brady Taylor, Deliang Fan and Yiran Chen, \u201cImproving the Efficiency of In-Memory-Computing Macro with a Hybrid Analog-Digital Computing Mode for Lossless Neural Network Inference\u201d In: 61st Design Automation Conference (DAC)<\/em>, San Francisco, CA, June 23-27, 2024 [pdf<\/a>]<\/li>\n\n\n\n
  17. [CICC\u201924<\/strong>] Amitesh Sridharan, Fan Zhang, Jae-sun Seo, Deliang Fan, \u201cSP-IMC: A Sparsity Aware In-Memory-Computing Macro in 28nm CMOS with Configurable Sparse Representation for Highly Sparse DNN Workloads,\u201d IEEE Custom Integrated Circuits Conference (CICC)<\/em>, 21 – 24 April 2024, Denver, CO. [pdf<\/a>]<\/li>\n\n\n\n
  18. [AAAI\u201924<\/strong>] Jingtao Li, Xing Chen, Li Yang, Adnan Siraj Rakin, Deliang Fan, and Chaitali Chakrabarti, \u201cEMGAN: Early-Mix-GAN on Extracting Server-side Model in Split Federated Learning,\u201d Thirty-Eighth AAAI Conference on Artificial Intelligence<\/em> (AAAI), Feb. 20-27, 2024, Vancouver, BC, Canada. [pdf]<\/a><\/li>\n\n\n\n
  19. [S&P\u201924]<\/strong> Yukui Luo, Adnan Siraj Rakin, Deliang Fan, and Xiaolin Xu, \u201cDeepShuffle: A Lightweight Defense Framework against Adversarial Fault Injection Attacks on Deep Neural Networks in Multi-Tenant Cloud-FPGA,\u201d 45th IEEE Symposium on Security and Privacy (S&P)<\/em>, San Francisco, CA, May 20-23, 2024 [pdf]<\/a> [video<\/a>]<\/li>\n\n\n\n
  20. [NeurIPS\u201923<\/strong>] Jian Meng, Li Yang, Kyungmin Lee, Jinwoo Shin, Deliang Fan, and Jae-sun Seo, \u201cSlimmed Asymmetrical Contrastive Learning and Cross Distillation for Lightweight Model Training,\u201d Thirty-Seventh Conference on Neural Information Processing Systems (NeurIPS)<\/em>, New Orleans, LA, Dec. 2023 [pdf]<\/a><\/li>\n\n\n\n
  21. [ESSCIRC\u201923<\/strong>] Fan Zhang, Wangxin He, Injune Yeo, Maximilian Liehr, Nathaniel Cady, Yu Cao, Jae-sun Seo, and Deliang Fan, \u201cA 65nm RRAM Compute-in-Memory Macro for Genome Sequencing Alignment,\u201d 49th European Solid-State Circuits Conference (ESSCIRC)<\/em>, Lisbon, Portugal, Sep. 11-14, 2023 [pdf]<\/a><\/li>\n\n\n\n
  22. [ESSCIRC\u201923<\/strong>] Jyotishman Saikia, Amitesh Sridharan, Injune Yeo, Shreyas Venkataramanaiah, Deliang Fan, Jae-sun Seo, \u201cFP-IMC: a 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro,\u201d 49th European Solid-State Circuits Conference (ESSCIRC)<\/em>, Lisbon, Portugal, Sep. 11-14, 2023 [pdf]<\/a><\/li>\n\n\n\n
  23. [DAC\u201923<\/strong>] Amitesh Sridharan, Fan Zhang, Yang Sui, Bo Yuan and Deliang Fan, \u201cDSPIMM: Digital Sparse In-Memory matrix vector multiplier for Communication Applications\u201d In: 60th Design Automation Conference (DAC)<\/em>, San Francisco, CA, July 9-13, 2023 [pdf]<\/a><\/li>\n\n\n\n
  24. [GLSVLSI\u201923<\/strong>] Nakul Kochar, Lucas Ekiert, Deniz Najafi, Deliang Fan, and Shaahin Angizi. \u201cAccelerating Low Bit-width Neural Networks at the Edge, PIM or FPGA: A Comparative Study,\u201d In 33rd edition of Great Lakes Symposium on VLSI (GLSVLSI)<\/em>, June 5-7, 2023, Knoxville, TN, USA [pdf]<\/a><\/li>\n\n\n\n
  25. [VLSI-TSA\u201923<\/strong>] Zhenyu Wang, Pragnya Sudershan Nalla, Gokul Krishnan, Rajiv V Joshi, Nathaniel C Cady, Deliang Fan, Jae-sun Seo, Yu Cao, \u201cDigital-Assisted Analog In-Memory Computing with RRAM Devices,\u201d 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA\/VLSI-DAT)<\/em>, April, 2023 [pdf]<\/a><\/li>\n\n\n\n
  26. [NeurIPS\u201922<\/strong>] Li Yang*, Jian Meng*, Jae-sun Seo, and Deliang Fan, \u201cGet More at Once: Alternating Sparse Training with Gradient Correction,\u201d Thirty-sixth Conference on Neural Information Processing Systems (NeurIPS)<\/em>, New Orleans, LA, Nov.29 \u2013 Dec.1, 2022 (* The first two authors contribute equally) [pdf]<\/a> [open source code<\/a>]<\/li>\n\n\n\n
  27. [NeurIPS\u201922<\/strong>] Sen Lin, Li Yang, Deliang Fan, and Junshan Zhang, \u201cBeyond Not-Forgetting: Continual Learning with Backward Knowledge Transfer,\u201d Thirty-sixth Conference on Neural Information Processing Systems (NeurIPS)<\/em>, New Orleans, LA, Nov.29 \u2013 Dec.1, 2022 [pdf]<\/a><\/li>\n\n\n\n
  28. [ESWEEK\u201922<\/strong>] Gokul Krishnan, Zhenyu Wang, Injune Yeo, Li Yang, Jian Meng, Maximilian Liehr, Rajiv Joshi, Nathaniel C. Cady, Deliang Fan, Jae-sun Seo, and Yu Cao, \u201cHybrid RRAM\/SRAM In-Memory Computing for Robust DNN Acceleration,\u201d International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), associated with Embedded Systems Week (ESWEEK)<\/em>, , Hybrid-Shanghai, October 7-14, 2022 [pdf]<\/a><\/li>\n\n\n\n
  29. [ESSCIRC\u201922<\/strong>] Amitesh Sridharan*, Shaahin Angizi*, Sai Kiran Cherupally, Fan Zhang, Jae-sun Seo, and Deliang Fan, \u201cA 1.23-GHz 16-Kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm,\u201d 48th European Solid-State Circuits Conference (ESSCIRC)<\/em>, Milan, Italy, Sep. 19-22, 2022 (* The first two authors contribute equally) [pdf]<\/a><\/li>\n\n\n\n
  30. [ACSSC\u201922<\/strong>]Fan Zhang, Li Yang, and Deliang Fan, \u201cEfficient Multi-task Adaption for Crossbar-based In-Memory Computing,\u201d 2022 56th Asilomar Conference on Signals, Systems, and Computers<\/em>, Oct. 2022 [pdf]<\/a><\/li>\n\n\n\n
  31. [ICSICT\u201922<\/strong>] Gokul Krishnan, Zhenyu Wang, Li Yang, Injune Yeo, Jian Meng, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-sun Seo, Yu Cao \u201cIMC Architecture for Robust DNN Acceleration,\u201d In 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)<\/em>, Oct. 25-28, 2022. [pdf]<\/a><\/li>\n\n\n\n
  32. [S&P\u201922<\/strong>] Adnan Siraj Rakin*, Md Hafizul Islam Chowdhuryy*, Fan Yao, and Deliang Fan, , \u201cDeepSteal: Advanced Model Extractions Leveraging Efficient Weight Stealing in Memories,\u201d 43rd IEEE Symposium on Security and Privacy (S&P)<\/em>, San Francisco, CA, May 23-26, 2022 (* The first two authors contribute equally) [Top Picks in Hardware and Embedded Security<\/strong> in 2024 ] [pdf]<\/a> [open source code<\/a>] [video<\/a>]<\/li>\n\n\n\n
  33. [CVPR\u201922<\/strong>] Li Yang, Adnan Siraj Rakin, and Deliang Fan, \u201cRep-Net: Efficient On-Device Learning via Feature Reprogramming\u201d IEEE\/CVF Conference on Computer Vision and Pattern Recognition (CVPR)<\/em>, New Orleans, Louisiana, June 19-24, 2022 [pdf]<\/a> [open source code<\/a>]<\/li>\n\n\n\n
  34. [CVPR\u201922<\/strong>] Jian Meng, Li Yang, Jinwoo Shin, Deliang Fan, and Jae-sun Seo, \u201cContrastive Dual Gating: Learning Sparse Features With Contrastive Learning\u201d IEEE\/CVF Conference on Computer Vision and Pattern Recognition (CVPR)<\/em>, New Orleans, Louisiana, June 19-24, 2022 [pdf]<\/a><\/li>\n\n\n\n
  35. [CVPR\u201922<\/strong>] Jingtao Li, Adnan Siraj Rakin, Xing Chen, Zhezhi He, Deliang Fan, and Chaitali Chakrabarti, \u201cResSFL: A Resistance Transfer Framework for Defending Model Inversion Attack in Split Federated Learning\u201d IEEE\/CVF Conference on Computer Vision and Pattern Recognition (CVPR)<\/em>, New Orleans, Louisiana, June 19-24, 2022 [pdf]<\/a><\/li>\n\n\n\n
  36. [CVPR-ECV\u201922<\/strong>] Li Yang, Adnan Siraj Rakin, and Deliang Fan, \u201cDA3 : Dynamic Additive Attention Adaption for Memory-Efficient On-Device Learning\u201d Efficient Deep Learning for Computer Vision CVPR Workshop, <\/em>, New Orleans, Louisiana, June 19-24, 2022 [pdf]<\/a><\/li>\n\n\n\n
  37. [DAC\u201922<\/strong>] Fan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Cao, and Deliang Fan, \u201cXMA: A Crossbar-aware Multi-task Adaption Framework via Shift-based Mask Learning Method\u201d In: 59th Design Automation Conference (DAC)<\/em>, San Francisco, CA, July 10-14, 2022 [pdf]<\/a><\/li>\n\n\n\n
  38. [GLSVLSI\u201922<\/strong>] Amitesh Sridharan*, Fan Zhang*, and Deliang Fan. \u201cMnM: A Fast and Efficient Min\/Max Searching in MRAM ,\u201d In 32nd edition of Great Lakes Symposium on VLSI (GLSVLSI)<\/em>, Irvine, CA, June 6-8, 2022 (*first two authors contribute equally) [pdf]<\/a><\/li>\n\n\n\n
  39. [ICLR\u201922<\/strong>] Sen Li, Li Yang, Deliang Fan, and Junshan Zhang, \u201cTRGP: Trust Region Gradient Projection for Continual Learning,\u201d The Tenth International Conference on Learning Representations,<\/em> (ICLR), Apr. 25- 29th , 2022 [pdf] <\/a>(-spotlight-)<\/strong><\/li>\n\n\n\n
  40. [AAAI\u201922<\/strong>] Jingbo Sun, Li Yang, Jiaxin Zhang, Frank Liu, Mahantesh Halappanavar, Deliang Fan, and Yu Cao, \u201cGradient-based Novelty Detection Boosted by Self-supervised Binary Classification,\u201d Thirty-Six AAAI Conference on Artificial Intelligence<\/em> (AAAI), Feb. 22-March 1, 2022, Vancouver, BC, Canada [pdf]<\/a><\/li>\n\n\n\n
  41. [DATE\u201922<\/strong>] Fan Zhang, Li Yang, Jian Meng, Yu Cao, Jae-sun Seo, and Deliang Fan, \u201cXST: A Crossbar Column-wise Sparse Training for Efficient Continual Learning,\u201d Design, Automation and Test in Europe<\/em> (DATE), 14 \u2013 23 March 2022 [pdf] <\/a>( \u2013Best IP Paper Award\u2013<\/strong>)<\/li>\n\n\n\n
  42. [ASPDAC\u201922]<\/strong>  Fan Zhang, Li Yang, Jian Meng, Yu Cao, Jae-sun Seo, and Deliang Fan, \u201cXBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption,\u201d  27th Asia and South Pacific Design Automation Conference (ASPDAC)<\/em>, Jan. 17-20, 2022 [pdf]<\/a><\/li>\n\n\n\n
  43. [HOST\u201921]<\/strong>  Jingtao Li, Zhezhi He, Adnan Siraj Rakin, Deliang Fan and Chaitali Chakrabarti, \u201cNeurObfuscator: A Full-stack Obfuscation Tool to Mitigate Neural Architecture Stealing,\u201d  In 2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)<\/em>, Washington DC, USA, June 27-30, 2022 [pdf]<\/a><\/li>\n\n\n\n
  44. [ICCAD\u201921]<\/strong>  Arman Roohi, MohammadReza Taheri, Shaahin Angizi and Deliang Fan, \u201cRNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems,\u201d  In 2021 International Conference on Computer Aided Design (ICCAD)<\/em>, Nov. 1-4, 2021 [pdf]<\/a><\/li>\n\n\n\n
  45. [MASS\u201921]<\/strong>  Sen Lin, Li Yang, Zhezhi He, Deliang Fan and Junshan Zhang, \u201cMetaGater: Fast Learning of Conditional Channel Gated Networks via Federated Meta-Learning,\u201d In 2021 IEEE 18th International Conference on Mobile Ad Hoc and Smart Systems (MASS)<\/em>, Oct. 4-7, 2021 (Invited) [pdf]<\/a><\/li>\n\n\n\n
  46. [USENIX Security\u201921]<\/strong>  Adnan Siraj Rakin*, Yukui Luo*, Xiaolin Xu and Deliang Fan, \u201cDeep-Dup: An Adversarial Weight Duplication Attack Framework to Crush Deep Neural Network in Multi-Tenant FPGA,\u201d In 30th USENIX Security Symposium<\/em>, August 11-13, 2021 (*first two authors contribute equally); [pdf]<\/a> [open source code<\/a>] [video<\/a>]<\/li>\n\n\n\n
  47. [CVPR\u201921<\/strong>] Li Yang, Zhezhi He, Junshan Zhang and Deliang Fan, \u201cKSM: Fast Multiple Task Adaption via Kernel-wise Soft Mask Learning\u201d IEEE\/CVF Computer Vision and Pattern Recognition (CVPR)<\/em>, June 19-25, 2021 [pdf]<\/a> [open source code<\/a>]<\/li>\n\n\n\n
  48. [DAC\u201921<\/strong>] Fan Zhang, Shaahin Angizi and Deliang Fan, \u201cMax-PIM: Fast and Efficient Max\/Min Searching in DRAM\u201d In: 58th Design Automation Conference (DAC)<\/em>, San Francisco, CA, Dec. 5-9, 2021 [pdf] <\/a>( \u2013Best Paper Candidate Nomination \u2014<\/strong>)<\/li>\n\n\n\n
  49. [DAC\u201921<\/strong>] Fan Zhang, Shaahin Angizi, Naima Ahmed Fahmi, Wei Zhang and Deliang Fan, \u201cPIM-Quantifier: A Processing-in-Memory Platform for Genome Quantification\u201d. In: 58th Design Automation Conference (DAC)<\/em>, San Francisco, CA, Dec. 5-9, 2021 [pdf]<\/a><\/li>\n\n\n\n
  50. [DAC\u201921<\/strong>] Sai Kiran Cherupally, Adnan Rakin, Shihui Yin, Mingoo Seok, Deliang Fan and Jae-sun Seo. \u201cLeveraging Variability and Aggressive Quantization of In-Memory Computing for Robustness Improvement of Deep Neural Network Hardware Against Adversarial Input and Weight Attacks\u201d. In: 58th Design Automation Conference (DAC)<\/em>, San Francisco, CA, Dec. 5-9, 2021 [pdf]<\/a><\/li>\n\n\n\n
  51. [GLSVLSI\u201921<\/strong>] Shaahin Angizi, Arman Roohi, Mohammadreza Taheri and Deliang Fan. \u201cProcessing-in-Memory Acceleration of MAC based Applications Using Residue Number System: A Comparative Study,\u201d In 31st edition of Great Lakes Symposium on VLSI (GLSVLSI)<\/em>, June 22-25, 2021 [pdf]<\/a><\/li>\n\n\n\n
  52. [ISCAS\u201921<\/strong>] Jian Meng, Li Yang, Xiaochen Peng, Shimeng Yu, Deliang Fan, Jae-Sun Seo, \u201cStructured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks,\u201d IEEE International Symposium on Circuits and Systems (ISCAS)<\/em> (ISCAS), May, 2021 [pdf-journal version]<\/a><\/li>\n\n\n\n
  53. [IRPS\u201921<\/strong>] Wangxi He, Wonbo Shim, Shihui Yin, Xiaoyu Sun, Deliang Fan, Shimeng Yu, Jae-sun Seo, \u201cCharacterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing,\u201d IEEE International Reliability Physics Symposium, <\/em>(IRPS), March 21-25, 2021 ( \u2013Best Student Paper Candidate\u2013<\/strong>) [pdf]<\/a><\/li>\n\n\n\n
  54. [DATE\u201921<\/strong>] Jingtao Li, Adnan Siraj Rakin, Zhezhi He, Deliang Fan and Chaitali Chakrabarti, \u201cRADAR: Run-time Adversarial Weight Attack Detection and Accuracy Recovery,\u201d Design, Automation and Test in Europe<\/em> (DATE), 01-05 Feb. 2021, ALPEXPO, Grenoble, France [pdf]<\/a><\/li>\n\n\n\n
  55. [ASPDAC\u201921<\/strong>]  Li Yang, and Deliang Fan, \u201cDynamic Neural Network to Enable Run-Time Trade-off between Accuracy and Latency,\u201d 26th Asia and South Pacific Design Automation Conference (ASPDAC)<\/em>, Jan. 18-21, 2021 (invited) [pdf]<\/a><\/li>\n\n\n\n
  56. [SOCC\u201920<\/strong>]  Li Yang, Zhezhi He, Shaahin Angizi and Deliang Fan, \u201cProcessing-In-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency,\u201d 33rd IEEE International System-on-Chip Conference (SOCC)<\/em>, September 8-11, 2020 (invited) [pdf]<\/a><\/li>\n\n\n\n
  57. [USENIX Security\u201920]<\/strong>  Fan Yao, Adnan Siraj Rakin and Deliang Fan, \u201cDeepHammer: Depleting the Intelligence of Deep Neural Networks through Targeted Chain of Bit Flips,\u201d In 29th USENIX Security Symposium (USENIX Security 20)<\/em>, August 12-14, 2020, Boston, MA, USA [pdf] <\/a> [video<\/a>] <\/li>\n\n\n\n
  58. [ISLPED<\/strong>\u201920] Mingyen Lee, Wenjun Tang, Bowen Xue, Juejian Wu, Mingyuan Ma, Yu Wang, Yongpan Liu, Deliang Fan, Vijaykrishnan Narayanan, Huazhong Yang and Xueqing Li, \u201cFeFET-Based Low-Power Bitwise Logic-in-Memory with Direct Write-Back and Data-Adaptive Dynamic Sensing Interface\u201d, ACM\/IEEE International Symposium on Low Power Electronics and Design<\/em>, August 10-12, 2020 [pdf]<\/a><\/li>\n\n\n\n
  59. [GLSVLSI\u201920<\/strong>] Shaahin Angizi, Wei Zhang and Deliang Fan, \u201cExploring DNA Alignment-in-Memory Leveraging EmergingSOT-MRAM\u201d, 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI<\/em>), September 7-9, 2020 (invited) [pdf]<\/a><\/li>\n\n\n\n
  60. [GLSVLSI\u201920<\/strong>] Adnan Siraj Rakin, Zhezhi He, Li Yang, Yanzhi Wang, Liqiang Wang, Deliang Fan, \u201cRobust Sparse Regularization: Simultaneously Optimizing Neural Network Robustness and Compactness\u201d, 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI<\/em>), September 7-9, 2020 (invited) [pdf]<\/a><\/li>\n\n\n\n
  61. [GLSVLSI\u201920<\/strong>] Baogang Zhang, Necati Uysal, Deliang Fan and Rickard Ewetz, \u201cRedundant Neurons and Shared Redundant Synapses for Robust Memristor-based DNNs with Reduced Overhead\u201d, 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI<\/em>), September 7-9, 2020 [pdf]<\/a><\/li>\n\n\n\n
  62. [GLSVLSI\u201920<\/strong>] Dayane Reis, Di Gao, Shaahin Angizi, Xunzhao Yin, Deliang Fan, Michael Niemier, Cheng Zhuo and X. Sharon Hu, \u201cModeling and benchmarking computing-in-memory for design space exploration\u201d, 30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI<\/em>), September 7-9, 2020 (invited) [pdf]<\/a><\/li>\n\n\n\n
  63. [CVPR\u201920]<\/strong>  Adnan Siraj Rakin, Zhezhi He and Deliang Fan, \u201cTBT: Targeted Neural Network Attack with Bit Trojan,\u201d 2020 IEEE\/CVF Conference on Computer Vision and Pattern Recognition (CVPR)<\/em>, June 16-18, 2020, Seattle, Washington, USA [pdf] <\/a>[open source code] <\/a> <\/li>\n\n\n\n
  64. [CVPR\u201920]<\/strong>  Zhezhi He\uff0cAdnan Siraj Rakin, Jingtao Li, Chaitali Chakrabarti and Deliang Fan, \u201cDefending and Harnessing the Bit-Flip based Adversarial Weight Attack,\u201d 2020 IEEE\/CVF Conference on Computer Vision and Pattern Recognition (CVPR)<\/em>, June 16-18, 2020, Seattle, Washington, USA [pdf] <\/a>[open source code] <\/a> <\/li>\n\n\n\n
  65. [DAC\u201920<\/strong>] Li Yang, Zhezhi He, Yu Cao and Deliang Fan. \u201cNon-uniform DNN Structured Subnets Sampling for Dynamic Inference\u201d. In: 57th Design Automation Conference (DAC)<\/em>, San Francisco, CA, July 19-23, 2020. [pdf]<\/a><\/li>\n\n\n\n
  66. [DAC\u201920<\/strong>] Shaahin Angizi, Naima Ahmed Fahmi, Wei Zhang and Deliang Fan, \u201cPIM-Assembler: A Processing-in-Memory Platform for Genome Assembly\u201d In: 57th Design Automation Conference (DAC)<\/em>, San Francisco, CA, July 19-23, 2020. [pdf]<\/a><\/li>\n\n\n\n
  67. [DAC\u201920<\/strong>] Jingtao Li, Adnan Siraj Rakin, Yan Xiong, Liangliang Chang, Zhezhi He, Deliang Fan, and Chaitali Chakrabarti. \u201cDefending Bit-Flip Attack through DNN Weight Reconstruction\u201d. In: 57th Design Automation Conference (DAC)<\/em>, San Francisco, CA, July 19-23, 2020. [pdf]<\/a><\/li>\n\n\n\n
  68. [AAAI\u201920<\/strong>] Li Yang, Zhezhi He and Deliang Fan, \u201cHarmonious Coexistence of Structured Weight Pruning and Ternarization for Deep Neural Networks,\u201d Thirty-Fourth AAAI Conference on Artificial Intelligence<\/em> (AAAI), Feb. 7-12 2020, New York, USA (-spotlight-)<\/strong> [pdf]<\/a><\/li>\n\n\n\n
  69. [DATE\u201920<\/strong>] Shaahin Angizi, Jiao Sun, Wei Zhang and Deliang Fan, \u201cPIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence Alignment,\u201d Design, Automation and Test in Europe<\/em> (DATE), 09-13 March 2020, ALPEXPO, Grenoble, France [pdf]<\/a><\/li>\n\n\n\n
  70. [ASPDAC\u201920<\/strong>] Li Yang, Shaahin Angizi, Deliang Fan, \u201cA Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks,\u201d Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 13-16, 2020, Beijing, China [pdf] <\/a> <\/li>\n\n\n\n
  71. [ASPDAC\u201920<\/strong>] Baogang Zhang, Necati Uysal, Deliang Fan, Rickard Ewetz, \u201cRepresentable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors,\u201d Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 13-16, 2020, Beijing, China [pdf]<\/a><\/li>\n\n\n\n
  72. [ICCV\u201919]<\/strong> Adnan Siraj Rakin* , Zhezhi He*, Deliang Fan, \u201cBit-Flip Attack: Crushing Neural Network with Progressive Bit Search,\u201d IEEE International Conference on Computer Vision, Seoul, Korea, Oct 27 \u2013 Nov 3, 2019 [pdf] <\/a>(* The first two authors contributed equally) [open source code]<\/a><\/li>\n\n\n\n
  73. [ICCAD\u201919]<\/strong> Shaahin Angizi and Deliang Fan, \u201cReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations,\u201d IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 4-7 November 2019, Westminster, CO [pdf]<\/a><\/li>\n\n\n\n
  74. [NANOARCH\u201919<\/strong>] Shaahin Angizi and Deliang Fan, \u201cDeep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach?,\u201d IEEE\/ACM International Symposium on Nanoscale Architectures, 17-19 July 2019, Qingdao, CHINA [pdf]<\/a><\/li>\n\n\n\n
  75. [ISVLSI\u201919<\/strong>] Shaahin Angizi, Zhezhi He, Dayane Reis, Xiaobo Sharon Hu, Wilman Tsai, Shy Jay Lin and Deliang Fan, \u201cAccelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?,\u201d IEEE Computer Society Annual Symposium on VLSI, 15 \u2013 17 July 2019, Miami, Florida, USA (invited)[pdf]<\/a><\/li>\n\n\n\n
  76. [ISVLSI\u201919<\/strong>] Adnan Siraj Rakin and Deliang Fan, \u201cDefense-Net: Defend Against a Wide Range of Adversarial Attacks through Adversarial Detector,\u201d IEEE Computer Society Annual Symposium on VLSI, 15 \u2013 17 July 2019, Miami, Florida, USA [pdf]<\/a><\/li>\n\n\n\n
  77. [Dagstuhl Report\u201919<\/strong>] Deliang Fan, \u201cCognitive Computing-in-Memory: Circuit to Algorithm,\u201d Dagstuhl Seminar 19152, Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing, Germany, 2019 [pdf]<\/a><\/li>\n\n\n\n
  78. [DRC\u201919]<\/strong> Durjoy Dev, Adithi Krishnaprasad, Zhezhi He, Sonali Das, Mashiyat Sumaiya Shawkat, Madison Manley, Olaleye Aina, Deliang Fan, Yeonwoong Jung and Tania Roy, \u201cArtificial Neuron using Ag\/2D-MoS2\/Au Threshold Switching Memristor,\u201d 77th Device Research Conference, 23 \u2013 26 June 2019, University of Michigan, Ann Arbor [pdf]<\/a><\/li>\n\n\n\n
  79. [CVOPS\u201919<\/strong>] Yifan Ding, Liqiang Wang, Huan Zhang, Jinfeng Yi, Deliang Fan, and Boqing Gong, \u201cDefending Against Adversarial Attacks Using Random Forests,\u201d Workshop on The Bright and Dark Sides of Computer Vision: Challenges and Opportunities for Privacy and Security<\/em>, June 16-20, 2019, Long Beach, CA, USA [pdf]<\/a><\/li>\n\n\n\n
  80. [CVPR\u201919]<\/strong> Zhezhi He*, Adnan Siraj Rakin* and Deliang Fan, \u201cParametric Noise Injection: Trainable Randomness to Improve Deep Neural Network Robustness against Adversarial Attack,\u201d Conference on Computer Vision and Pattern Recognition (CVPR)<\/em>, June 16-20, 2019, Long Beach, CA, USA (* The first two authors contributed equally) [pdf]<\/a> [code in GitHub]<\/a><\/li>\n\n\n\n
  81. [CVPR\u201919]<\/strong> Zhezhi He and Deliang Fan, \u201cSimultaneously Optimizing Weight and Quantizer of Ternary Neural Network using Truncated Gaussian Approximation,\u201d Conference on Computer Vision and Pattern Recognition (CVPR)<\/em>, June 16-20, 2019, Long Beach, CA, USA [pdf]<\/a><\/li>\n\n\n\n
  82. [GLSVLSI\u201919<\/strong>] Shaahin Angizi and Deliang Fan, \u201cGraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing,\u201d ACM Great Lakes Symposium on VLSI(GLSVLSI)<\/em>, May 9-11, 2019, Washington, D.C. USA ( \u2013Best Paper Award\u2013<\/strong>) [pdf]<\/a><\/li>\n\n\n\n
  83. [GLSVLSI\u201919<\/strong>] Li Yang, Zhezhi He and Deliang Fan, \u201cBinarized Depthwise Separable Neural Network for Object Tracking in FPGA,\u201d ACM Great Lakes Symposium on VLSI(GLSVLSI)<\/em>, May 9-11, 2019, Washington, D.C. USA [pdf]<\/a><\/li>\n\n\n\n
  84. [DAC\u201919]<\/strong> Shaahin Angizi, Jiao Sun, Wei Zhang and Deliang Fan, \u201cAlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM,\u201d Design Automation Conference <\/em>(DAC), June 2-6, 2019, Las Vegas, NV, USA [pdf]<\/a><\/li>\n\n\n\n
  85. [DAC\u201919]<\/strong> Zhezhi He, Jie Lin, Rickard Ewetz, Jiann-Shiun Yuan and Deliang Fan, \u201cNoise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping,\u201d Design Automation Conference <\/em>(DAC), June 2-6, 2019, Las Vegas, NV, USA [pdf]<\/a> [open source code]<\/a><\/li>\n\n\n\n
  86. [ISQED\u201919<\/strong>] Arman Roohi, Shaahin Angizi, Deliang Fan and Ronald F DeMara, \u201cProcessing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency and Power-Intermittency Resilience,\u201d The 20th International Symposium on Quality Electronic Design<\/em> (ISQED), March 6-7, 2019, Santa Clara, CA, USA ( \u2013Best Paper Candidate\u2013<\/strong>)<\/li>\n\n\n\n
  87. [DATE\u201919]<\/strong> Shaahin Angizi, Jiao Sun, Wei Zhang and Deliang Fan, \u201cGraphS: A Graph Processing Accelerator Leveraging SOT-MRAM,\u201d Design, Automation and Test in Europe<\/em> (DATE), March 25-29, 2019, Florence, Italy. [pdf]<\/a><\/li>\n\n\n\n
  88. [WACV\u201919<\/strong>] Zhezhi He, Boqing Gong, Deliang Fan, \u201cOptimize Deep Convolutional Neural Network with Ternarized Weights and High Accuracy,\u201d IEEE Winter Conference on Applications of Computer Vision<\/em>, January 7-11, 2019, Hawaii, USA [pdf]<\/a>[open source code]<\/a><\/li>\n\n\n\n
  89. [ASPDAC\u201919<\/strong>] Shaahin Angizi, Zhezhi He and Deliang Fan, \u201cParaPIM: A Parallel Processing-in-Memory Accelerator for Binary-Weight Deep Neural Networks,\u201d Asia and South Pacific Design Automation Conference (ASP-DAC)<\/em>, Jan. 21-24, 2019, Tokyo, Japan [pdf]<\/a><\/li>\n\n\n\n
  90. [ASPDAC\u201919<\/strong>] Baogang Zhang, Necati Uysal, Deliang Fan, Rickard Ewetz, \u201cHandling Stuck-at-faults in Memristor Crossbar Arrays using Matrix Transformations,\u201d Asia and South Pacific Design Automation Conference (ASP-DAC)<\/em>, Jan. 21-24, 2019, Tokyo, Japan [pdf]<\/a>( \u2013Best Paper Candidate\u2013<\/strong>)<\/li>\n\n\n\n
  91. [ICCD\u201918<\/strong>] Adnan Siraj Rakin, Shaahin Angizi, Zhezhi He and Deliang Fan, \u201cPIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks,\u201d IEEE International Conference on Computer Design (ICCD) <\/em>, Oct. 7-10, 2018, Orlando, FL, USA [pdf]<\/a><\/li>\n\n\n\n
  92. [ICCAD\u201918]<\/strong> Shaahin Angizi, Zhezhi He and Deliang Fan, \u201cDIMA: A Depthwise CNN In-Memory Accelerator,\u201d IEEE\/ACM International Conference on Computer Aided Design<\/em>, Nov. 5-8, 2018, San Diego, CA, USA [pdf]<\/a><\/li>\n\n\n\n
  93. [ISLPED\u201918]<\/strong> Li Yang, Zhezhi He and Deliang Fan, \u201cA Fully Onchip Binarized Convolutional Neural Network FPGA Implementation with Accurate Inference,\u201d ACM\/IEEE International Symposium on Low Power Electronics and Design<\/em>, July 23-25, 2018, Bellevue, Washington, USA [pdf]<\/a><\/li>\n\n\n\n
  94. [ISVLSI\u201918<\/strong>] Zhezhi He, Shaahin Angizi, Adnan Siraj Rakin and Deliang Fan, \u201cBD-NET: A Multiplication-less DNN with Binarized Depthwise Separable Convolution,\u201d IEEE Computer Society Annual Symposium on VLSI<\/em>, July 9-11, 2018, Hong Kong, CHINA [pdf]<\/a> (\u2013Best Paper Award\u2013<\/strong>)<\/li>\n\n\n\n
  95. [ISVLSI\u201918<\/strong>] Zhezhi He, Shaahin Angizi and Deliang Fan, \u201cAccelerating Low Bit-Width Deep Convolution Neural Network in MRAM,\u201d IEEE Computer Society Annual Symposium on VLSI<\/em>, July 9-11, 2018, Hong Kong, CHINA (invited) [pdf]<\/a><\/li>\n\n\n\n
  96. [GLSVLSI\u201918<\/strong>] Shaahin Angizi, Zhezhi He, Yu Bai, Jie Han, Mingjie Lin and Deliang Fan, \u201cLeveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Network,\u201d ACM Great Lakes Symposium on VLSI <\/em>(GLSVLSI), Chicago, IL, USA, May 23-25, 2018 (invited) [pdf]<\/a><\/li>\n\n\n\n
  97. [DAC\u201918]<\/strong> Shaahin Angizi*, Zhezhi He*, Adnan Siraj Rakin and Deliang Fan, \u201cCMP-PIM: An Energy-Efficient Comparator-based Processing-In-Memory Neural Network Accelerator,\u201d IEEE\/ACM Design Automation Conference <\/em>(DAC), June 24-28, 2018, San Francisco, CA, USA (* The first two authors contributed equally) [pdf]<\/a><\/li>\n\n\n\n
  98. [DAC\u201918]<\/strong> Shaahin Angizi, Zhezhi He and Deliang Fan, \u201cPIMA-Logic: A Novel Processing-in-Memory Architecture for Highly Flexible and Energy-Efficient Logic Computation, \u201d IEEE\/ACM Design Automation Conference <\/em>(DAC), June 24-28, 2018, San Francisco, CA, USA [pdf]<\/a><\/li>\n\n\n\n
  99. [WACV\u201918<\/strong>] Y. Ding, L. Wang, D. Fan and B. Gong \u201cA Semi-Supervised Two-Stage Approach to Learning from Noisy Labels,\u201d IEEE Winter Conference on Applications of Computer Vision<\/em>, March 12-14, 2018, Stateline, NV, USA [pdf]<\/a><\/li>\n\n\n\n
  100. [ASPDAC\u201918<\/strong>] F. Parveen, Z. He, S. Angizi and D. Fan, \u201cHieIM: Highly Flexible In-Memory Computing using STT MRAM,\u201d Asia and South Pacific Design Automation Conference (ASP-DAC)<\/em>, Jan. 22-25, 2018, Jeju Island, Korea [pdf]<\/a><\/li>\n\n\n\n
  101. [ASPDAC\u201918<\/strong>] S. Angizi, Z. He, F. Parveen and D. Fan, \u201cIMCE: Energy-Efficient Bit-Wise In-Memory Convolution Engine for Deep Neural Network,\u201d Asia and South Pacific Design Automation Conference (ASP-DAC)<\/em>, Jan. 22-25, 2018, Jeju Island, Korea [pdf]<\/a><\/li>\n\n\n\n
  102. [ICCD\u201917<\/strong>] Z. He, S. Angizi and D. Fan, \u201cExploring STT-MRAM based In-Memory Computing Paradigm with Application of Image Edge Extraction,\u201d IEEE International Conference on Computer Design (ICCD) <\/em>, Nov. 5-8, 2017, Boston, MA [pdf]<\/a><\/li>\n\n\n\n
  103. [ICCD\u201917<\/strong>] D. Fan and S. Angizi \u201cEnergy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM,\u201d IEEE International Conference on Computer Design (ICCD) <\/em>, Nov. 5-8, 2017, Boston, MA [pdf]<\/a><\/li>\n\n\n\n
  104. [NCAMA\u201917<\/strong>] S. Angizi and D. Fan , \u201cIMC: Energy-Efficient In-Memory Convolver for Accelerating Binarized Deep Neural Network,\u201d Neuromorphic Computing Symposium: Architectures, Models, and Applications <\/em>, July 17-19, 2017, Knoxville, Tennessee [pdf]<\/a><\/li>\n\n\n\n
  105. [ICCAD\u201917]<\/strong> M. Yang, J. Hayes, D. Fan and W. Qian, \u201cDesign of Accurate Stochastic Number Generators with Noisy Emerging Devices for Stochastic Computing,\u201d IEEE\/ACM International Conference on Computer Aided Design<\/em>, Nov 13-16, Irvin, CA [pdf]<\/a><\/li>\n\n\n\n
  106. [ISLPED\u201917]<\/strong> F. Parveen, S. Angizi, Z. He and D. Fan , \u201cLow Power In-Memory Computing based on Dual-Mode SOT-MRAM,\u201d IEEE\/ACM International Symposium on Low Power Electronics and Design<\/em>, July 24-26, 2017, Taipei, Taiwan [pdf]<\/a><\/li>\n\n\n\n
  107. [NANOARCH\u201917<\/strong>] Z. He, S. Angizi, F. Parveen and D. Fan , \u201cHigh Performance and Energy-Efficient In-Memory Computing Architecture based on SOT-MRAM,\u201d IEEE\/ACM International Symposium on Nanoscale Architectures <\/em>, July 25-26, 2017, Newport, USA [pdf]<\/a><\/li>\n\n\n\n
  108. [ISVLSI\u201917<\/strong>] D. Fan, S. Angizi and Z. He, \u201cIn-Memory Computing with Spintronic Devices,\u201d IEEE Computer Society Annual Symposium on VLSI (ISVLSI)<\/em>, July 3-5, 2017, Bochum, Germany (invited) [pdf]<\/a><\/li>\n\n\n\n
  109. [ISVLSI\u201917<\/strong>] S. Angizi, Z. He, F. Parveen and D. Fan, \u201cRIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device,\u201d IEEE Computer Society Annual Symposium on VLSI (ISVLSI)<\/em>, July 3-5, 2017, Bochum, Germany [pdf]<\/a><\/li>\n\n\n\n
  110. [ISVLSI\u201917<\/strong>] F. Parveen, Z. He, S. Angizi and D. Fan, \u201cHybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device,\u201d IEEE Computer Society Annual Symposium on VLSI (ISVLSI)<\/em>, July 3-5, 2017, Bochum, Germany [pdf]<\/a> ( \u2013Best Paper Award\u2013<\/strong>)<\/li>\n\n\n\n
  111. [MWSCAS\u201917<\/strong>] D. Fan, Z. He and S. Angizi, \u201cLeveraging Spintronic Devices for Ultra-Low Power In-Memory Computing: Logic and Neural Network,\u201d 60th IEEE International Midwest Symposium on Circuits and Systems<\/em>, Aug. 6-9, 2017, Boston, MA, USA (invited) [pdf]<\/a><\/li>\n\n\n\n
  112. [ISCAS\u201917]<\/strong> F. Parveen, S. Angizi, Z. He and D. Fan, \u201cHybrid Polymorphic Logic Gate Using 6 Terminal Magnetic Domain Wall Motion Device,\u201d IEEE International Symposium on Circuits & Systems (ISCAS)<\/em>, Baltimore, MD, USA, May 28-31, 2017 [pdf]<\/a><\/li>\n\n\n\n
  113. [GLSVLSI\u201917<\/strong>] Z. He, S. Angizi, F. Parveen, and D. Fan, \u201cLeveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-Memory Data Encryption\u201d, 27th GLSVLSI<\/em>, Banff, Alberta, Canada, May 10-12, 2017 [pdf]<\/a><\/li>\n\n\n\n
  114. [GLSVLSI\u201917<\/strong>] S. Angizi, Z. He, and D. Fan, \u201cEnergy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices\u201d, 27th GLSVLSI<\/em>, Banff, Alberta, Canada, May 10-12, 2017 [pdf]<\/a><\/li>\n\n\n\n
  115. [GLSVLSI\u201917<\/strong>] Q. Alasad, J. Yuan, and D. Fan, \u201cLeveraging All-Spin Logic to Improve Hardware Security\u201d, 27th GLSVLSI<\/em>, Banff, Alberta, Canada, May 10-12, 2017 [pdf]<\/a><\/li>\n\n\n\n
  116. [DATE\u201917]<\/strong> Z. He, D. Fan, \u201cA Tunable Magnetic Skyrmion Neuron Cluster for Energy Efficient Artificial Neural Network,\u201d Design, Automation and Test in Europe (DATE)<\/em>, Lausanne, Switzerland, 27-31 March, 2017 [pdf]<\/a><\/li>\n\n\n\n
  117. [ISQED\u201917<\/strong>] S. Angizi, Z. He, R. DeMara and D. Fan, \u201cComposite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing,\u201d 18th International Symposium on Quality Electronic Design(ISQED)<\/em>, Santa Clara, CA, USA, 13-15 March, 2017[pdf]<\/a><\/li>\n\n\n\n
  118. [ISLPED\u201916]<\/strong> Z. He and D. Fan, \u201cA Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator\u201d, International Symposium on Low Power Electronics and Design (ISLPED)<\/em>, San Francisco, CA, Aug. 8-10, 2016[pdf]<\/a><\/li>\n\n\n\n
  119. [NANOARCH\u201916<\/strong>] D. Fan, \u201cLow Power In-Memory Computing Platform with Four Terminal Magnetic Domain Wall Motion Devices\u201d, IEEE\/ ACM International Symposium on Nanoscale Architectures<\/em>, , Beijing, China, July 18-20, 2016 [pdf]<\/a><\/li>\n\n\n\n
  120. [GLSVLSI\u201916<\/strong>] D. Fan, \u201c Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate\u201d, 26th GLSVLSI<\/em>, Boston, Massachusetts, May 18-20, 2016[pdf]<\/a><\/li>\n\n\n\n
  121. [IJCNN\u201916<\/strong>] C. Liyanagedera, K. Yogendra, K. Roy and D. Fan, \u201c Spin Torque Nano-Oscillator based Oscillatory Neural Network\u201d, 2016 IEEE International Joint Conference on Neural Network (IJCNN)<\/em>, Vancouver, Canada, July 24-29, 2016[pdf]<\/a><\/li>\n\n\n\n
  122. [ASPDAC\u201916<\/strong>] K. Yogendra, D. Fan, Y. Shim, M. Koo, and K. Roy, \u201c Computing with Coupled Spin Torque Nano Oscillators\u201d, 21st Asia and South Pacific Design Automation Conference (ASP-DAC)<\/em>, Macao, China, Jan. 25-28, 2016[pdf]<\/a><\/li>\n\n\n\n
  123. [ASPDAC\u201916<\/strong>] A. Sengupta, K. Yogendra, D. Fan and K. Roy, \u201cProspects of efficient neural computing with arrays of magneto-metallic neurons and synapses\u201d, 21st Asia and South Pacific Design Automation Conference (ASP-DAC)<\/em>, Macao, China, Jan. 25-28, 2016[pdf]<\/a><\/li>\n\n\n\n
  124. [DATE\u201914]<\/strong> K. Roy, M. Sharad, D. Fan and K. Yogendra, \u201cBrain-inspired computing with spin torque devices\u201d, Design, Automation & Test in Europe (DATE)<\/em>, 2014. (invited tutorial)[pdf]<\/a><\/li>\n\n\n\n
  125. [ISVLSI\u201914<\/strong>] K. Roy, M. Sharad, D. Fan and K. Yogendra, \u201cComputing with Spin-Transfer-Torque Devices: Prospects and Perspectives,\u201d IEEE Computer Society Annual Symposium on VLSI (ISVLSI)<\/em>, Tampa, FL, July 9-11, 2014 (special session paper)[pdf]<\/a><\/li>\n\n\n\n
  126. [DAC\u201913]<\/strong> M. Sharad, D. Fan, and K. Roy, \u201cUltra Low Power Associative Computing With Spin Neurons and Resistive Crossbar Memory,\u201d IEEE\/ACM Design Automation Conference (DAC)<\/em>, Austin, TX, June 2-6, 2013[pdf]<\/a><\/li>\n\n\n\n
  127. [ISLPED\u201913]<\/strong> K. Roy, M. Sharad, D. Fan, and K. Yogendra, \u201cBeyond Charge-Base Computing: Boolean and Non Boolean computing Using spin Devices,\u201d International Symposium on Low Power and Design (ISLPED)<\/em>, 2013. (invited tutorial)[pdf]<\/a><\/li>\n\n\n\n
  128. [ICCAD\u201913]<\/strong> K. Roy, M. Sharad, D. Fan, and K. Yogendra, \u201cExploring Boolean and Non Boolean Computing Using Spin torque Switches\u201d International Conference on Computer-Aided Design (ICCAD)<\/em>, 2013. (invited tutorial)[pdf]<\/a><\/li>\n\n\n\n
  129. [ISQED\u201913<\/strong>] M. Sharad, D. Fan, and K. Roy, \u201cLow Power and Compact Mixed-Mode Signal Processing Hardware using Spin-Neurons,\u201d IEEE International Symposium on Quality Electronic Design (ISQED)<\/em>, Santa Clara, CA, March 4-6, 2013[pdf]<\/a><\/li>\n\n\n\n
  130. [E3S\u201913<\/strong>] M. Sharad, D. Fan, K. Yogendra, and K. Roy, \u201cUltra-Low Power Neuromorphic Computing with Spin-Torque Devices,\u201d 3rd Berkeley Symposium on Energy Efficient Electronic Systems<\/em>, 2013[pdf]<\/a><\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":381,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-1513","page","type-page","status-publish","hentry"],"acf":[],"yoast_head":"\nConference Proceedings - Deliang Fan<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/faculty.engineering.asu.edu\/dfan\/conference-proceedings\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Conference Proceedings - Deliang Fan\" \/>\n<meta property=\"og:url\" content=\"https:\/\/faculty.engineering.asu.edu\/dfan\/conference-proceedings\/\" \/>\n<meta property=\"og:site_name\" content=\"Deliang Fan\" \/>\n<meta property=\"article:modified_time\" content=\"2026-04-24T04:12:49+00:00\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data1\" content=\"21 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/faculty.engineering.asu.edu\\\/dfan\\\/conference-proceedings\\\/\",\"url\":\"https:\\\/\\\/faculty.engineering.asu.edu\\\/dfan\\\/conference-proceedings\\\/\",\"name\":\"Conference Proceedings - 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